There are many computationally-intensive applications that hunger for
high-performance computer systems to manage their enormous memory
and processing requirements. There is a need for a scalable,
massively-parallel processing supercomputer that can satisfy this
hunger. Developing such an architecture requires evaluation of hard
data when making design decisions. Software-based simulations can be
helpful, but a physical implementation of the hardware runs faster and
can reveal fatal flaws that were overlooked. It also grounds the
design in reality. Since fabrication of a chip implementing a brand
new architecture is not immediately feasible, the use of configurable
logic devices is favored. This thesis presents an implementation of
the ARIES Hamal Parallel Computer architecture, targeted at FPGA
configurable logic devices. This experience revealed that although
FPGAs are extremely flexible devices, synthesis of a complete
processor is a time-consuming task and that the logic capacity of
typical FPGAs are insufficient for processors with very large (128-bit)
data paths.