\* This neighborhood allows us to work with lattice gases that have 2 bits moving in each of 4 directions. It partitions the 8-bit LGA sites into 1x4 or 4x1 blocks. Since 4 8-bit sites is too much to fit into one 16-bit cell, we break the updating into 4 phases: north-table acts on a row of 4 adjacent north-going components south-table acts on a row of 4 adjacent south-going components east-table acts on a col of 4 adjacent east-going components west-table acts on a col of 4 adjacent west-going components This neighborhood could be used, for example, to implement a version of the billiard-ball model, by simply having particles collide with a separation of 2 between them. *\ \* For display, we will arrange the bits in 2x2 blocks, 8 bits/site, divided up between two subcells. *\ 0 subcell: 00 00 == ul.nw 01 01 == ur.nw 02 02 == ll.nw 03 03 == lr.nw 04 04 == ul.ne 05 05 == ur.ne 06 06 == ll.ne 07 07 == lr.ne 08 08 == ul.se 09 09 == ur.se 10 10 == ll.se 11 11 == lr.se 12 12 == ul.sw 13 13 == ur.sw 14 14 == ll.sw 15 15 == lr.sw 00 03 == n.west 04 07 == n.east 08 11 == s.east 12 15 == s.west 1 subcell: 00 00 == ul.se' 01 01 == ur.se' 02 02 == ll.se' 03 03 == lr.se' 04 04 == ul.sw' 05 05 == ur.sw' 06 06 == ll.sw' 07 07 == lr.sw' 08 08 == ul.nw' 09 09 == ur.nw' 10 10 == ll.nw' 11 11 == lr.nw' 12 12 == ul.ne' 13 13 == ur.ne' 14 14 == ll.ne' 15 15 == lr.ne' 00 03 == s.east' 04 07 == s.west' 08 11 == n.west' 12 15 == n.east' \* When updating a 4x1 block, c0.nw is the first bit of column 0 that is heading in the north-west direction, c0.nw' is the second bit of column 0 heading in this direction, etc. *\ 0 subcell: 00 00 == c0.nw 01 01 == c1.nw 02 02 == c2.nw 03 03 == c3.nw 04 04 == c0.ne 05 05 == c1.ne 06 06 == c2.ne 07 07 == c3.ne 08 08 == c0.se 09 09 == c1.se 10 10 == c2.se 11 11 == c3.se 12 12 == c0.sw 13 13 == c1.sw 14 14 == c2.sw 15 15 == c3.sw 1 subcell: 00 00 == c0.se' 01 01 == c1.se' 02 02 == c2.se' 03 03 == c3.se' 04 04 == c0.sw' 05 05 == c1.sw' 06 06 == c2.sw' 07 07 == c3.sw' 08 08 == c0.nw' 09 09 == c1.nw' 10 10 == c2.nw' 11 11 == c3.nw' 12 12 == c0.ne' 13 13 == c1.ne' 14 14 == c2.ne' 15 15 == c3.ne' \* When updating a 1x4 block, r0.nw is the first bit of row 0 that is heading in the north-west direction, r0.nw' is the second bit of row 0 heading in this direction, etc. *\ 0 subcell: 00 00 == r0.nw 01 01 == r2.nw 02 02 == r1.nw 03 03 == r3.nw 04 04 == r0.ne 05 05 == r2.ne 06 06 == r1.ne 07 07 == r3.ne 08 08 == r0.se 09 09 == r2.se 10 10 == r1.se 11 11 == r3.se 12 12 == r0.sw 13 13 == r2.sw 14 14 == r1.sw 15 15 == r3.sw 1 subcell: 00 00 == r0.se' 01 01 == r2.se' 02 02 == r1.se' 03 03 == r3.se' 04 04 == r0.sw' 05 05 == r2.sw' 06 06 == r1.sw' 07 07 == r3.sw' 08 08 == r0.nw' 09 09 == r2.nw' 10 10 == r1.nw' 11 11 == r3.nw' 12 12 == r0.ne' 13 13 == r2.ne' 14 14 == r1.ne' 15 15 == r3.ne' 0 7 == cell-lo 0 0 == cell-lo-0 1 1 == cell-lo-1 8 15 == cell-hi 8 8 == cell-hi-0 9 9 == cell-hi-1 0 constant nc 1 constant top/bottom 2 constant left/right : assemble-rule cell-hi top/bottom = if ul.nw <-> ll.nw ur.nw <-> lr.nw ul.ne <-> ll.ne ur.ne <-> lr.ne then cell-lo top/bottom = if ul.se <-> ll.se ur.se <-> lr.se ul.sw <-> ll.sw ur.sw <-> lr.sw then cell-hi left/right = if ul.nw <-> ur.nw ll.nw <-> lr.nw ul.ne <-> ur.ne ll.ne <-> lr.ne then cell-lo left/right = if ul.se <-> ur.se ll.se <-> lr.se ul.sw <-> ur.sw ll.sw <-> lr.sw then ; create-lut atab ?rule>table assemble-rule atab create-lut east-table create-lut west-table create-lut north-table create-lut south-table : do-north { n.west n.east n.west' n.east' } assemble-fields kick ul.nw field -1 x ur.nw field -1 x ul.ne field -1 x ur.ne field -1 x ul.nw' field -1 x ur.nw' field -1 x ul.ne' field -1 x ur.ne' field -1 x site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-0 field address sa-bit 0 reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-0 field address sa-bit 0 reg! kick run lut-data north-table switch-luts kick ul.nw field 1 x ur.nw field 1 x ul.ne field 1 x ur.ne field 1 x ul.nw' field 1 x ur.nw' field 1 x ul.ne' field 1 x ur.ne' field 1 x site-src lut lut-src site run switch-luts kick ul.nw field -1 x* ur.nw field -1 x* ul.ne field -1 x* ur.ne field -1 x* ul.nw' field -1 x* ur.nw' field -1 x* ul.ne' field -1 x* ur.ne' field -1 x* site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-0 field address sa-bit 0 reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-0 field address sa-bit 0 reg! kick run kick n.west field -1 x* -1 y* n.west' field -1 x* -1 y* n.east field 1 x* -1 y* n.east' field 1 x* -1 y* site-src site run reset-kicks ; : do-south { s.east' s.west' s.east s.west } assemble-fields kick ul.sw field -1 x ur.sw field -1 x ul.se field -1 x ur.se field -1 x ul.sw' field -1 x ur.sw' field -1 x ul.se' field -1 x ur.se' field -1 x site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-0 field address sa-bit 0 reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-0 field address sa-bit 0 reg! kick run lut-data south-table switch-luts kick ul.sw field 1 x ur.sw field 1 x ul.se field 1 x ur.se field 1 x ul.sw' field 1 x ur.sw' field 1 x ul.se' field 1 x ur.se' field 1 x site-src lut lut-src site run switch-luts kick ul.sw field -1 x* ur.sw field -1 x* ul.se field -1 x* ur.se field -1 x* ul.sw' field -1 x* ur.sw' field -1 x* ul.se' field -1 x* ur.se' field -1 x* site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-0 field address sa-bit 0 reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-0 field address sa-bit 0 reg! kick run kick s.west field -1 x* 1 y* s.west' field -1 x* 1 y* s.east field 1 x* 1 y* s.east' field 1 x* 1 y* site-src site run reset-kicks ; : do-east { s.east' n.east s.east n.east' } assemble-fields kick ul.se field -1 y ll.se field -1 y ul.ne field -1 y ll.ne field -1 y ul.se' field -1 y ll.se' field -1 y ul.ne' field -1 y ll.ne' field -1 y site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-1 field address sa-bit U log reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-1 field address sa-bit U log reg! kick run lut-data east-table switch-luts kick ul.se field 1 y ll.se field 1 y ul.ne field 1 y ll.ne field 1 y ul.se' field 1 y ll.se' field 1 y ul.ne' field 1 y ll.ne' field 1 y site-src lut lut-src site run switch-luts kick ul.se field -1 y* ll.se field -1 y* ul.ne field -1 y* ll.ne field -1 y* ul.se' field -1 y* ll.se' field -1 y* ul.ne' field -1 y* ll.ne' field -1 y* site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-1 field address sa-bit U log reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-1 field address sa-bit U log reg! kick run kick s.east field 1 x* 1 y* s.east' field 1 x* 1 y* n.east field 1 x* -1 y* n.east' field 1 x* -1 y* site-src site run reset-kicks ; : do-west { n.west s.west' n.west' s.west } assemble-fields kick ul.sw field -1 y ll.sw field -1 y ul.nw field -1 y ll.nw field -1 y ul.sw' field -1 y ll.sw' field -1 y ul.nw' field -1 y ll.nw' field -1 y site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-1 field address sa-bit U log reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-1 field address sa-bit U log reg! kick run lut-data west-table switch-luts kick ul.sw field 1 y ll.sw field 1 y ul.nw field 1 y ll.nw field 1 y ul.sw' field 1 y ll.sw' field 1 y ul.nw' field 1 y ll.nw' field 1 y site-src lut lut-src site run switch-luts kick ul.sw field -1 y* ll.sw field -1 y* ul.nw field -1 y* ll.nw field -1 y* ul.sw' field -1 y* ll.sw' field -1 y* ul.nw' field -1 y* ll.nw' field -1 y* site-src lut cell-hi field site lut-src site cell-hi field 0 fix cell-hi-1 field address sa-bit U log reg! run site-src lut cell-lo field site lut-src site cell-lo field 0 fix cell-lo-1 field address sa-bit U log reg! kick run kick s.west field -1 x* 1 y* s.west' field -1 x* 1 y* n.west field -1 x* -1 y* n.west' field -1 x* -1 y* site-src site run reset-kicks ; define-step full-step lut-data atab switch-luts do-north do-south do-east do-west 0 activate-subcell end-step this is macro-step 4 updates/macro define-step north-step lut-data atab switch-luts do-north 0 activate-subcell end-step define-step south-step lut-data atab switch-luts do-south 0 activate-subcell end-step define-step east-step lut-data atab switch-luts do-east 0 activate-subcell end-step define-step west-step lut-data atab switch-luts do-west 0 activate-subcell end-step : micro-step step-count @ 4 mod {{ north-step south-step east-step west-step }} ; this is update-step \* Note: macro step stuff should probably be fixed so that when you switch from micro to macro, the right number of micro steps get executed to start you on an even macro-step boundary. *\ \* Do a version of the BBM as a test of this neighborhood. *\