#!/bin/csh -f

alias BEGIN 'cat <<END'


set ctopa = "ctlsvtop"
set ctopb = "ctlsvtop"
set ftop = "fsmtop"
set dtopa = "datatop"
set dtopb = "datatop"
foreach arg ($*)
  if ($arg =~ fullctlsva) then
    set ctopa = "chip"
  else if ($arg =~ fullctlsvb) then
    set ctopb = "chip"
  else if ($arg =~ fullfsm) then
    set ftop = "chip"
  else if ($arg =~ fulldataa) then
    set dtopa = "chip"
  else if ($arg =~ fulldatab) then
    set dtopb = "chip"
  endif
end


BEGIN
/*	Interface board	model */

\`timescale 1 ns / 10 ps

module iboard (sb_clk, sb_as_, sb_pa, sb_d, sb_siz, sb_rd,
		sb_ack_, sb_merr_, sb_br_, sb_bg_, sb_sel_, 
		sb_irq_, sb_reset_n, sb_ext, parity,
		pb_d, pb_rst_, 
		pb_iosel, pb_eofout,
		pb_clk, pb_eosi, pb_eofin, pb_sync);

	/******************** I/O Declarations ******************************/

	input	sb_clk;			//	Clock from System
	inout	sb_as_;			//	Address Strobe from System
	inout	[27:0] sb_pa;	//	Phys. Adress bus from System
	inout	[31:0] sb_d;	//	Data Bus from System/Master/Slave
	inout	[2:0] sb_siz;	//	Transfer Size from System/Master
	inout	sb_rd;			//	Read from System/Master
	inout	[2:0] sb_ack_;	//	Acknowledge bits
	inout	sb_merr_;		//	LateError_ in new spec
	inout	[7:0] sb_br_;	//	Bus Request from Master
	inout	[7:0] sb_bg_;	//	Bus Grant from System
	inout	[7:0] sb_sel_;	//	Select from System
	inout	[7:1] sb_irq_;	//	Interrupt Requests from Master/Slave
	input	sb_reset_n;		//	Reset from System
	inout	sb_ext;			//	parity bit: see Assignments below...
	input	parity;			//	1=auto-parity generation; 0=sb_ext never driven


	// Pbus signals
	inout [15:0]
		pb_d;
	output
		pb_rst_,
		pb_eofout,
		pb_iosel,
		pb_sync;
	input
		pb_clk,
		pb_eosi,
		pb_eofin;


	// Internal signals
	wire [1:0]
		sva,
		pc;
	wire [2:0]
		sc,
		ackout,
		ack;
	wire
		int_imm,
		sclr_n,
		sbus_err,
		immed,
		pldec,
		op_data,
		ps8,
		p_rd,
		pdav_a;

	// This is the slot assigned to the interface
	parameter
		slot = 1 ;

	ni01d1 U200 (sel_high, 1'b1) ;
	ni01d1 U201 (sel_low, 1'b0) ;
	ni01d1 U202 (high, 1'b1) ;
	ni01d1 U203 (low, 1'b0) ;

	$ctopa U1
		(
		.p27(sb_d[31]), .p28(sb_d[30]),
		.p29(sb_d[29]), .p30(sb_d[28]),
		.p31(sb_d[27]), .p32(sb_d[26]),
		.p33(sb_d[25]), .p34(sb_d[24]),
		.p35(sb_d[23]), .p36(sb_d[22]),
		.p37(sb_d[21]), .p38(sb_d[20]),
		.p39(sb_d[19]), .p40(sb_d[18]),
		.p41(sb_d[17]), .p42(sb_d[16]),
		.p51(immed),		// int_imm_c
		.p47(hsync),		// imm_sync_c
		.p48(pb_eofin),		// eofin
		.p11(donep),		// donep_c
		.p43(flg8),		// cw_flg8_c
		.p44(p_rd),		// p_rd_c (output)
		// .p49,		// incout_c
		// .p45,		// hstop_c
		.p12(hnp_sel),		// hnp_sel_c
		.p46(ifc_rst_n),	// od_ri_c
		.p23(pb_rst_),		// psd_rc_c
		.p53(sb_pa [3]), .p14(sb_pa [2]),
		.p17(sc [2]), .p18(sc [1]), .p19(sc [0]),
		.p3(pdec_0),		// zin_c
		.p2(low),		// tst_c
		.p4(sb_bg_ [slot]),	// sb_bg_n_c
		.p26(pb_clk), .p9(ldctl), .p20(sld),
		.p1(high),		// sel_c
		.p8(low),		// op_shift_c (%changed)
		.p16(inca16),		// incadr_c
		.p7(tmint), .p6(pb_eosi), .p15(sbus_err),
		.p10(sv_en), .p50(sv_ld), .p21(pldec),
		.p25(sclr_n), .p13(sb_clk),
		// .p52,		// clr_suspend_c
		// .p5,			// partial_xfer_c
		// .p22,		// suspend_c
		.p24(pb_sync),		// sync_out_c
		.p55(sel_high), .p54(sel_high)
		) ;

	$ctopb U2
		(
		.p27(sb_d[15]), .p28(sb_d[14]),
		.p29(sb_d[13]), .p30(sb_d[12]),
		.p31(sb_d[11]), .p32(sb_d[10]),
		.p33(sb_d[9]), .p34(sb_d[8]),
		.p35(sb_d[7]), .p36(sb_d[6]),
		.p37(sb_d[5]), .p38(sb_d[4]),
		.p39(sb_d[3]), .p40(sb_d[2]),
		.p41(sb_d[1]), .p42(sb_d[0]),
		.p51(sb_irq_ [1]),	// int_imm_c
		.p47(immed),		// imm_sync_c
		.p48(pb_eofin),		// eofin
		.p11(pdec_0),		// donep_c
		.p43(cw),		// cw_flg8_c
		.p44(p_rd),		// p_rd_c (input)
		.p49(inca16),		// incout_c
		.p45(hstop),		// hstop_c
		.p12(hnp_sel),		// hnp_sel_c
		.p46(op_data),		// od_ri_c
		.p23(psd),		// psd_rc_c
		.p53(sb_pa [3]), .p14(sb_pa [2]),
		.p17(sc [2]), .p18(sc [1]), .p19(sc [0]),
		.p3(donep),		// zin_c
		.p2(low),		// tst_c
		.p4(sb_bg_ [slot]),	// sb_bg_n_c
		.p26(pb_clk), .p9(ldctl), .p20(sld),
		.p1(low),		// sel_c
		.p8(op_shift),		// op_shift_c
		.p16(incadr),		// incadr_c
		.p7(tmint), .p6(pb_eosi), .p15(sbus_err),
		.p10(sv_en), .p50(sv_ld), .p21(pldec),
		.p25(sclr_n), .p13(sb_clk),
		.p52(clr_suspend),	// clr_suspend_c
		.p5(partial_xfer),	// partial_xfer_c
		.p22(suspend),		// suspend_c
		.p24(hsync),		// sync_out_c
		.p55(sel_high), .p54(sel_high)
		) ;

	 $ftop U3 (
		.p2(sb_ack_[2]), .p3(sb_ack_[1]), .p4(sb_ack_[0]),
		.p31(sc [2]), .p32(sc [1]), .p33(sc [0]),
		.p45(pc [1]), .p46(pc [0]),
		// .p5(param_dr_n),
		.p34(incadr), .p30(sld),
		.p52(sb_rd), .p27(sb_br_ [slot]), .p11(sdr),
		.p9(ptr_inc),
		.p22(prom_dr_n), .p36(sv_en),
		.p48(sv_ld), .p39(pldec), .p23(pb_eofout),
		.p24(pb_iosel), .p37(ldctl), .p8(op_shift),
		.p40(pcwr), .p47(tmint), .p44(dr), .p41(pspty),
		.p42(ps16), .p43(ps8), .p35(sbus_err), 
		.p6(pb_eosi), .p50(sclr_n), .p16(sb_bg_ [slot]),
		.p49(p_rd), .p15(hstop), .p21(immed), .p29(cw),
		.p13(sb_clk), .p14(sb_pa [16]), .p10(sv_sel),
		.p20(donep), .p7(sv_on), .p26(pb_clk), .p28(flg8),
		.p18(pdav), .p12(pb_eofin), .p19(psd), .p38(sb_merr_),
		.p17(clr_suspend), .p1(suspend), .p51(partial_xfer),
		.p53(sb_reset_n), .p25(ifc_rst_n),
		.p55(sel_high), .p54(sel_low)
		) ;

	$dtopa U4 (
		.p5(pb_d [15]), .p6(pb_d [14]),
		.p7(pb_d [13]), .p8(pb_d [12]),
		.p9(pb_d [7]), .p10(pb_d [6]),
		.p11(pb_d [5]), .p12(pb_d [4]),
		.p27(sb_d [31]), .p28(sb_d [30]),
		.p29(sb_d [29]), .p30(sb_d [28]),
		.p31(sb_d [23]), .p32(sb_d [22]),
		.p33(sb_d [21]), .p34(sb_d [20]),
		.p35(sb_d [15]), .p36(sb_d [14]),
		.p37(sb_d [13]), .p38(sb_d [12]),
		.p39(sb_d [7]), .p40(sb_d [6]),
		.p41(sb_d [5]), .p42(sb_d [4]),
		.p1(sv_on), .p49(sv_sel),
		.p24(ptr_inc),
		.p45(op_shift),
		.p2(sb_siz [2]), .p3(sb_siz [1]), .p4(sb_siz [0]),
		.p16(sc [2]), .p17(sc [1]), .p18(sc [0]),
		.p46(pc [1]), .p47(pc [0]),
		.p51(sb_sel_ [slot]), .p52(sb_as_), .p44(flg8),
		.p23(pspty), .p22(ps16), .p21(ps8), .p19(dr),
		.p26(pb_clk), .p25(sclr_n), .p13(sb_clk), .p15(sld),
		.p14(sdr), .p20(immed), .p50(pb_eofout),
		.p48(pb_eofin), .p43(op_data), .p53(sb_bg_ [slot]),
		.p55(sel_low), .p54(sel_high)
		) ;

	$dtopb U5 (
		.p5(pb_d [11]), .p6(pb_d [10]),
		.p7(pb_d [9]), .p8(pb_d [8]),
		.p9(pb_d [3]), .p10(pb_d [2]),
		.p11(pb_d [1]), .p12(pb_d [0]),
		.p27(sb_d [27]), .p28(sb_d [26]),
		.p29(sb_d [25]), .p30(sb_d [24]),
		.p31(sb_d [19]), .p32(sb_d [18]),
		.p33(sb_d [17]), .p34(sb_d [16]),
		.p35(sb_d [11]), .p36(sb_d [10]),
		.p37(sb_d [9]), .p38(sb_d [8]),
		.p39(sb_d [3]), .p40(sb_d [2]),
		.p41(sb_d [1]), .p42(sb_d [0]),

		// not used
//		.p1(sv_on_a), .p49(sv_sel_a),
		.p24(ptr_inc),
//		.p2(sb_siz [2]), .p3(sb_siz [1]), .p4(sb_siz [0]),

		.p45(op_shift),
		.p16(sc [2]), .p17(sc [1]), .p18(sc [0]),
		.p46(pc [1]), .p47(pc [0]),
		.p51(sb_sel_ [slot]), .p52(sb_as_), .p44(flg8),
		.p23(pspty), .p22(ps16), .p21(ps8), .p19(dr),
		.p26(pb_clk), .p25(sclr_n), .p13(sb_clk), .p15(sld),
		.p14(sdr), .p20(immed), .p50(pb_eofout),
		.p48(pb_eofin), .p43(op_data), .p53(sb_bg_ [slot]),
		.p55(sel_low), .p54(sel_high)
		) ;


	        prom U6 (sb_pa [27:0], sb_d [31:24], prom_dr_n) ;

/*
	initial
		begin
                force U1.sb_clk_n_d = 1;
                force U1.sb_clk_n_f = 1;
                force U1.sclr_n_f = 0;
                force U1.sclr_n_d = 0;

                force U2.pb_clk_d = 0;
                force U2.pb_clk_n_f = 1;
                force U2.sclr_n_f = 0;
                force U2.sclr_n_d = 0;

                force U3.pb_clk_d = 0;
                force U3.pb_clk_c = 0;
                force U3.sclr_n_c = 0;
                force U3.sclr_n_d = 0;

                force U4.pb_clk_c = 0;
                force U4.pb_clk_n_f = 1;
                force U4.sclr_n_c = 0;
                force U4.sclr_n_f = 0;

                force U5.pb_clk_c = 0;
                force U5.pb_clk_n_f = 1;
                force U5.sclr_n_c = 0;
                force U5.sclr_n_f = 0;
		end
*/

endmodule


module bsel (i, out,
	o, e, sl) ;

	output [3:0]
		i;
	output
		out;
	input [3:0]
		o,
		e;
	input [1:0]
		sl;

	de24d1 U1 (i[0], i[1], i[2], i[3], sl [0], sl [1], u1en);

	mx41d1 U5 (u5z, o[0], o[1], o[2], o[3], sl [0], sl [1]);
	mx41d1 U18 (u18z, e[0], e[1], e[2], e[3], sl [0], sl [1]);
	in01d1 U29 (u29z, u18z) ;

	pc6s45 U28 (u1en, out, u5z, u29z);

endmodule


module osel (out, o, sl) ;

	output
		out;
	input [3:0]
		o;
	input [1:0]
		sl;

	mx41d1 U5 (u5z, o[0], o[1], o[2], o[3], sl [0], sl [1]);

	pc6o01 U6 (out, u5z, 1'b0);

endmodule

END

