	defparam
		U8.boxes = boxes,
		U8.mpb = mpb,
		U8.cpm = cpm;

	reg	sb_clk;			// Clock from System
	tri     sb_as_;			// Address Strobe from System
	tri     [27:0] sb_pa;	// Phys. Adress bus from System
	tri     [31:0] sb_d;	// Data Bus from System/Master/Slave
	tri     [2:0] sb_siz;	// Transfer Size from System/Master
	tri     sb_rd;			// Read from System/Master
	tri     [2:0] sb_ack_;	// Acknowledge bits
	tri     sb_merr_;		// LateError_ in new spec
	tri     [7:0] sb_br_;	// Bus Request from Master
	tri     [7:0] sb_bg_;	// Bus Grant from System
	tri     [7:0] sb_sel_;	// Select from System
	tri     [7:1] sb_irq_;	// Interrupt Requests from Master/Slave
	reg     sb_reset_;		// Reset from System
	tri     sb_ext;			// parity bit: see Assignments below...
	reg     parity;			// 1=auto-parity generation; 0=sb_ext never driven

	// Pbus signals
	tri [15:0]
		pb_dl,
		pb_dr;
	wire
		pb_rst_n,
		pb_eofout,
		pb_iosel,
		pb_status,
		pb_eofin,
		pb_sync;	// Encoded sync

	reg
		pb_clk;

	// DRAM signals
	wire [10:0]
		da0,             // DRAM address
		da1;

	// SRAM signals
	wire
		sad0_out,	// SRAM-A rdata
		sbd0_out,	// SRAM-B data
		mpa1,	// SRAM multipurpose control
		mpb1,	// SRAM multipurpose control
		sad00_in,		// SRAM-A rdata
		sbd00_in,		// SRAM-B data
		sad01_in,
		sbd01_in,
		sad02_in,
		sbd02_in,
		sad03_in,
		sbd03_in,

		sad1,
		sbd1;

	// data bus after first node
	tri [15:0]
		n_dl,
		n_dr;
	reg
		loop_mode,	// set to 1 if +loop command line arg
		idebug,		// set to 1 if +debug or +idebug command line arg
		cdebug,		// set to 1 if +debug or +cdebug command line arg
		vectors,	// set to 1 if +vectors command line arg
		ivectors,	// set to 1 if +ivectors command line arg
		random_delay;	// set to 1 if +random command line arg

	// Pullups
	assign (pull0, pull1) sb_bg_ = 8'hff ;
	assign (pull0, pull1) sb_br_ = 8'hff ;
	assign (pull0, pull1) sb_sel_ = 8'hff ;
	assign (pull0, pull1) sb_irq_ = 7'h7f ;
//	assign (pull0, pull1) sb_ack_ = 3'h7 ;
	assign (pull0, pull1) sb_siz = 3'h7 ;
//	assign (pull0, pull1) sb_rd = 1'h1 ;
//	assign (pull0, pull1) sb_merr_ = 1'h1 ;
	assign (pull0, pull1) pb_dl = 16'hffff ;
	assign (pull0, pull1) pb_dr = 16'hffff ;

	iboard U1 (sb_clk, sb_as_, sb_pa,
		sb_d, sb_siz, sb_rd,
		sb_ack_, sb_merr_, sb_br_, sb_bg_, sb_sel_, 
		sb_irq_, sb_reset_, sb_ext, parity,
		pb_dl, pb_rst_n, 
		pb_iosel, pb_eofout,
		pb_clk, pb_status, pb_eofin, pb_sync);

	SBUSD U2 (sb_clk, sb_as_, sb_pa, sb_d, sb_siz, sb_rd,
		sb_ack_, sb_merr_, sb_br_, sb_bg_, sb_sel_,
		sb_irq_, sb_reset_, sb_ext, parity);

	SBUSM U3 (sb_clk, sb_as_, sb_pa, sb_d, sb_siz, sb_rd,
		sb_ack_, sb_merr_, sb_br_, sb_bg_, sb_sel_,
		sb_irq_, sb_reset_, sb_ext, parity);

	ifcout #(cycle) U100 () ;
	cam00out #(cycle) U101 () ;
//	cam10out #(cycle) U102 () ;
        slaveout U104 () ;


	test #(cycle) U5 (loop_mode) ;

	halt #(cycle) U7 () ;

	cvout U9 ();

	header U8 () ;


	// CAM module
	wire [cpm - 1:0]
		disp,
		glue05_out,
		glue04_out,
		glue03_out,
		glue02_out,
		glue01_out,
		glue00_out;

	wire [cpm - 1:0]
		glue05_in = glue04_out,
		glue04_in = glue05_out,
		glue03_in = glue02_out,
		glue02_in = glue03_out,
		glue01_in = glue00_out,
		glue00_in = glue01_out;

	wire [cpm - 1:0]
		fly_out0;
	wire [cpm - 1:0]
		fly_in0 = fly_out0;
 
	wire [mpb -1:0]
		rsout,
		lsout,
		ioout,
		cam_status;

	cammod #(cpm) U00 (fly_out0, disp, cam_status [0], lsout [0],
		rsout [0], pb_dl [cpm - 1:0], pb_dr [cpm - 1:0],
		glue05_out, glue04_out, glue03_out,
		glue02_out, glue01_out, glue00_out,
		glue05_in, glue04_in, glue03_in,
		glue02_in, glue01_in, glue00_in,
		pb_eofout, 1'b0, pb_iosel, fly_in0,
		pb_rst_n, pb_clk,
		pb_sync, ioout [0]
		) ;

		// Add pullups
/*		assign (pull0, pull1) glue05_in = 16'hffff ;
		assign (pull0, pull1) glue04_in = 16'hffff ;
		assign (pull0, pull1) glue03_in = 16'hffff ;
		assign (pull0, pull1) glue02_in = 16'hffff ;
		assign (pull0, pull1) glue01_in = 16'hffff ;
		assign (pull0, pull1) glue00_in = 16'hffff ;
*/
		// module select (status) pins
		pullup (cam_status [0]) ;
/*		pulldown (cam_status [1]) ;
		pulldown (cam_status [2]) ;
		pulldown (cam_status [3]) ;
		pulldown (cam_status [4]) ;
		pulldown (cam_status [5]) ;
		pulldown (cam_status [6]) ;
		pulldown (cam_status [7]) ;
*/
		// lsout
		pulldown (lsout [0]) ;
/*		pulldown (lsout [1]) ;
		pulldown (lsout [2]) ;
		pulldown (lsout [3]) ;
		pulldown (lsout [4]) ;
		pulldown (lsout [5]) ;
		pulldown (lsout [6]) ;
		pulldown (lsout [7]) ;
*/
		// disp
		pulldown (disp [0]) ;
/*		pulldown (disp [1]) ;
		pulldown (disp [2]) ;
		pulldown (disp [3]) ;
		pulldown (disp [4]) ;
		pulldown (disp [5]) ;
		pulldown (disp [6]) ;
		pulldown (disp [7]) ;
*/

		assign pb_status = |(cam_status) ;

		assign pb_eofin = |(lsout) ;

	integer i;

	initial
		fork

			begin

			// display configuration
			U8.disp_config ;

			// check for loop mode
			if ($test$plusargs ("noloop") )
				loop_mode = 0;
			else
				begin
				loop_mode = 1;
				$display ("") ;
				$display ("***") ;
				$display ("*** Loop mode on") ;
				$display ("***") ;
				$display ("") ;
				end

			// check for interface debug mode
                        if (
			   $test$plusargs ("idebug") ||
			   $test$plusargs ("debug")
			   )
                                begin
				idebug = 1;
				$display ("") ;
				$display ("***") ;
                                $display ("*** Interface Debug mode on") ;
				$display ("***") ;
				$display ("") ;
                                end
			else
				idebug = 0;

			// check for cam debug mode
                        if (
			   $test$plusargs ("cdebug") ||
			   $test$plusargs ("debug")
			   )
                                begin
				cdebug = 1;
				$display ("") ;
				$display ("***") ;
                                $display ("*** Cam debug mode on") ;
				$display ("***") ;
				$display ("") ;
                                end
			else
				cdebug = 0;

			// check for cam vectors
                        if (
			   $test$plusargs ("vectors")
			   )
                                begin
				vectors = 1;
				$display ("") ;
				$display ("***") ;
                                $display ("*** Vector generation on") ;
				$display ("***") ;
				$display ("") ;
                                end
			else
				vectors = 0;

			// check for interface vectors
			if (
			   $test$plusargs ("ivectors")
			   )
				begin
				ivectors = 1;
				$display ("") ;
				$display ("***") ;
				$display ("*** Interface vector generation on") ;
				$display ("***") ;
				$display ("") ;
				end
			else
				ivectors = 0;

			U2.init_bus ;

			// check for random delays
			if (
			   $test$plusargs ("random")
			   )
				begin
				U2.precision = 0;
				$display ("") ;
				$display ("***") ;
				$display ("***  RANDOM SBUS DELAYS SELECTED ***") ;
				$display ("***") ;
				$display ("") ;
				end
			else
				U2.precision = 1;

			// set Translation Cycle delay (0 = random)
			//  this is commented out because of addition
			//  of +random option
//			U2.precision = 1 ;

			// choice of 5 cycle or 512 cycle SBus reset
			sb_reset_ = 0 ;
/*			for (i = 0; i < 512; i = i + 1)
				#cycle;
*/
			for (i = 0; i < 5; i = i + 1)
				#cycle;
			sb_reset_ = 1 ;
			#cycle;
			#cycle;

			// reset interface (1 cycle)
			U5.U1.cam_slave_wr (2'h1, 32'hc0000000) ;

			U5.do_test ;
			$finish (2);

			end

			// sb_clk = pb_clk
			forever
				begin
				#(cycle/4) sb_clk = 1 ;
				pb_clk = 1 ;
				#(cycle/2) sb_clk = 0 ;
				pb_clk = 0 ;
				#(cycle/4) ;
				end

			// fast pb_clk
/*			forever
				begin
				#(cycle/4) sb_clk = 1 ;
				pb_clk = 1 ;
				#(cycle/4) pb_clk = 0 ;
				#(cycle/4) sb_clk = 0 ;
				pb_clk = 1 ;
				#(cycle/4) pb_clk = 0 ;
				end
*/
			// slow pb_clk
/*			forever
				begin
				#(cycle/4) sb_clk = 1 ;
				pb_clk = 1 ;
				#(cycle/2) sb_clk = 0 ;
				#(cycle/4) ;
				#(cycle/4) sb_clk = 1 ;
				pb_clk = 0 ;
				#(cycle/2) sb_clk = 0 ;
				#(cycle/4) ;
				end
*/
		join
endmodule


END

