Reply to Mukesh's items of 10/20/93 Timing info: 1. Here are the delays from the sb_clk external pin to the sdav input to each of the davsync instances. After this is the delay from the sb_clk external pin to the clock input of the U9 flipflop in davsync. ******************************************************************************** VLSItv> show delay start P13 end u9.u72.u54.u1.u9.d Rising Output: 18.7ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 2.1[1.4] LSTC00: 1.9[1.2] 3.33 U1113.ZN=sb_clk_- n_f 3.0[2.1] IN01D5: .9[.8] 4.52 U9.U82.ZN 4.6[3.5] IN01D5: 1.3[1.3] 3.67 U9.U4.U27.U6.QN 7.8[3.9] DFPTNB: 3.2[.5] .64 U9.U4.U27.U13.ZN 8.8[4.8] IN01D3: 1.1[.9] 4.14 U9.U4.U4.u4.ZN 9.5[5.2] IN01D1: .6[.3] .35 U9.U4.U4.u6.ZN 10.3[5.7] ND04D1: .9[.6] .84 U9.U4.U4.U24.Z 12.3[5.8] OR03D1: 1.9[.1] .30 U9.U4.U4.U25.ZN 13.2[6.3] ND02D1: .9[.5] .43 U9.U4.U90.Z=sld_f 15.0[7.4] NI01D5: 1.9[1.1] 3.79 U9.U72.U61.ZN 15.4[7.6] ND02D1: .4[.1] .30 U9.U72.U29.Z0N 17.2[7.9] DE24D1: 1.8[.3] .40 U9.U72.U66.Z 18.2[8.3] AN02D1: 1.0[.4] .67 END U9.U72.U45.ZN 18.7[8.4] IN01D3: .4[.2] .61 Falling Output: 19.5ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 1.4[.6] LSTC00: 1.2[.5] 3.33 U1113.ZN=sb_clk_- n_f 3.1[2.1] IN01D5: 1.7[1.5] 4.52 U9.U82.ZN 4.3[3.0] IN01D5: 1.3[1.0] 3.67 U9.U4.U27.U6.QN 7.8[3.5] DFPTNB: 3.5[.5] .64 U9.U4.U27.U13.ZN 10.2[5.6] IN01D3: 2.4[2.1] 4.14 U9.U4.U4.u4.ZN 10.4[5.8] IN01D1: .3[.1] .35 U9.U4.U4.u6.ZN 11.9[6.7] ND04D1: 1.4[.9] .84 U9.U4.U4.u8.ZN 12.2[6.8] IN01D1: .3[.1] .28 U9.U4.U4.u9.ZN 13.6[7.8] ND03D1: 1.5[1.1] .86 U9.U4.U4.U25.ZN 14.2[8.2] ND02D1: .6[.3] .43 U9.U4.U90.Z=sld_f 16.0[8.8] NI01D5: 1.9[.7] 3.79 U9.U72.U61.ZN 16.6[9.0] ND02D1: .6[.1] .30 U9.U72.U29.Z0N 17.8[9.3] DE24D1: 1.2[.3] .40 U9.U72.U66.Z 19.3[10.2] AN02D1: 1.5[.9] .67 END U9.U72.U45.ZN 19.5[10.3] IN01D3: .2[.1] .61 ******************************************************************************** VLSItv> show delay start P13 end u9.u72.u54.u2.u9.d Rising Output: 18.1ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 2.1[1.4] LSTC00: 1.9[1.2] 3.33 U1113.ZN=sb_clk_- n_f 3.0[2.1] IN01D5: .9[.8] 4.52 U9.U82.ZN 4.6[3.5] IN01D5: 1.3[1.3] 3.67 U9.U4.U27.U6.QN 7.8[3.9] DFPTNB: 3.2[.5] .64 U9.U4.U27.U13.ZN 8.8[4.8] IN01D3: 1.1[.9] 4.14 U9.U4.U4.u4.ZN 9.5[5.2] IN01D1: .6[.3] .35 U9.U4.U4.u6.ZN 10.3[5.7] ND04D1: .9[.6] .84 U9.U4.U4.U24.Z 12.3[5.8] OR03D1: 1.9[.1] .30 U9.U4.U4.U25.ZN 13.2[6.3] ND02D1: .9[.5] .43 U9.U4.U90.Z=sld_f 15.0[7.4] NI01D5: 1.9[1.1] 3.79 U9.U72.U61.ZN 15.4[7.6] ND02D1: .4[.1] .30 U9.U72.U29.Z1N 17.7[8.5] DE24D1: 2.3[.9] .81 END U9.U72.U44.ZN 18.1[8.7] IN01D3: .5[.2] .62 Falling Output: 18.8ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 1.4[.6] LSTC00: 1.2[.5] 3.33 U1113.ZN=sb_clk_- n_f 3.1[2.1] IN01D5: 1.7[1.5] 4.52 U9.U82.ZN 4.3[3.0] IN01D5: 1.3[1.0] 3.67 U9.U4.U27.U6.QN 7.8[3.5] DFPTNB: 3.5[.5] .64 U9.U4.U27.U13.ZN 10.2[5.6] IN01D3: 2.4[2.1] 4.14 U9.U4.U4.u4.ZN 10.4[5.8] IN01D1: .3[.1] .35 U9.U4.U4.u6.ZN 11.9[6.7] ND04D1: 1.4[.9] .84 U9.U4.U4.u8.ZN 12.2[6.8] IN01D1: .3[.1] .28 U9.U4.U4.u9.ZN 13.6[7.8] ND03D1: 1.5[1.1] .86 U9.U4.U4.U25.ZN 14.2[8.2] ND02D1: .6[.3] .43 U9.U4.U90.Z=sld_f 16.0[8.8] NI01D5: 1.9[.7] 3.79 U9.U72.U61.ZN 16.6[9.0] ND02D1: .6[.1] .30 U9.U72.U29.Z1N 18.6[10.0] DE24D1: 2.0[1.0] .81 END U9.U72.U44.ZN 18.8[10.0] IN01D3: .2[.1] .62 ******************************************************************************** VLSItv> show delay start P13 end u9.u72.u54.u3.u9.d Rising Output: 17.8ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 2.1[1.4] LSTC00: 1.9[1.2] 3.33 U1113.ZN=sb_clk_- n_f 3.0[2.1] IN01D5: .9[.8] 4.52 U9.U82.ZN 4.6[3.5] IN01D5: 1.3[1.3] 3.67 U9.U4.U27.U6.QN 7.8[3.9] DFPTNB: 3.2[.5] .64 U9.U4.U27.U13.ZN 8.8[4.8] IN01D3: 1.1[.9] 4.14 U9.U4.U4.u4.ZN 9.5[5.2] IN01D1: .6[.3] .35 U9.U4.U4.u6.ZN 10.3[5.7] ND04D1: .9[.6] .84 U9.U4.U4.U24.Z 12.3[5.8] OR03D1: 1.9[.1] .30 U9.U4.U4.U25.ZN 13.2[6.3] ND02D1: .9[.5] .43 U9.U4.U90.Z=sld_f 15.0[7.4] NI01D5: 1.9[1.1] 3.79 U9.U72.U61.ZN 15.4[7.6] ND02D1: .4[.1] .30 U9.U72.U29.Z2N 17.4[8.2] DE24D1: 2.0[.7] .62 END U9.U72.U43.ZN 17.8[8.4] IN01D3: .4[.2] .60 Falling Output: 18.6ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 1.4[.6] LSTC00: 1.2[.5] 3.33 U1113.ZN=sb_clk_- n_f 3.1[2.1] IN01D5: 1.7[1.5] 4.52 U9.U82.ZN 4.3[3.0] IN01D5: 1.3[1.0] 3.67 U9.U4.U27.U6.QN 7.8[3.5] DFPTNB: 3.5[.5] .64 U9.U4.U27.U13.ZN 10.2[5.6] IN01D3: 2.4[2.1] 4.14 U9.U4.U4.u4.ZN 10.4[5.8] IN01D1: .3[.1] .35 U9.U4.U4.u6.ZN 11.9[6.7] ND04D1: 1.4[.9] .84 U9.U4.U4.u8.ZN 12.2[6.8] IN01D1: .3[.1] .28 U9.U4.U4.u9.ZN 13.6[7.8] ND03D1: 1.5[1.1] .86 U9.U4.U4.U25.ZN 14.2[8.2] ND02D1: .6[.3] .43 U9.U4.U90.Z=sld_f 16.0[8.8] NI01D5: 1.9[.7] 3.79 U9.U72.U61.ZN 16.6[9.0] ND02D1: .6[.1] .30 U9.U72.U29.Z2N 18.3[9.7] DE24D1: 1.7[.7] .62 END U9.U72.U43.ZN 18.6[9.7] IN01D3: .2[.1] .60 ******************************************************************************** VLSItv> show delay start P13 end u9.u72.u54.u4.u9.d Rising Output: 17.8ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 2.1[1.4] LSTC00: 1.9[1.2] 3.33 U1113.ZN=sb_clk_- n_f 3.0[2.1] IN01D5: .9[.8] 4.52 U9.U82.ZN 4.6[3.5] IN01D5: 1.3[1.3] 3.67 U9.U4.U27.U6.QN 7.8[3.9] DFPTNB: 3.2[.5] .64 U9.U4.U27.U13.ZN 8.8[4.8] IN01D3: 1.1[.9] 4.14 U9.U4.U4.u4.ZN 9.5[5.2] IN01D1: .6[.3] .35 U9.U4.U4.u6.ZN 10.3[5.7] ND04D1: .9[.6] .84 U9.U4.U4.U24.Z 12.3[5.8] OR03D1: 1.9[.1] .30 U9.U4.U4.U25.ZN 13.2[6.3] ND02D1: .9[.5] .43 U9.U4.U90.Z=sld_f 15.0[7.4] NI01D5: 1.9[1.1] 3.79 U9.U72.U61.ZN 15.4[7.6] ND02D1: .4[.1] .30 U9.U72.U29.Z3N 17.4[8.2] DE24D1: 2.0[.7] .65 END U9.U72.U42.ZN 17.8[8.4] IN01D3: .5[.2] .63 Falling Output: 18.6ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 1.4[.6] LSTC00: 1.2[.5] 3.33 U1113.ZN=sb_clk_- n_f 3.1[2.1] IN01D5: 1.7[1.5] 4.52 U9.U82.ZN 4.3[3.0] IN01D5: 1.3[1.0] 3.67 U9.U4.U27.U6.QN 7.8[3.5] DFPTNB: 3.5[.5] .64 U9.U4.U27.U13.ZN 10.2[5.6] IN01D3: 2.4[2.1] 4.14 U9.U4.U4.u4.ZN 10.4[5.8] IN01D1: .3[.1] .35 U9.U4.U4.u6.ZN 11.9[6.7] ND04D1: 1.4[.9] .84 U9.U4.U4.u8.ZN 12.2[6.8] IN01D1: .3[.1] .28 U9.U4.U4.u9.ZN 13.6[7.8] ND03D1: 1.5[1.1] .86 U9.U4.U4.U25.ZN 14.2[8.2] ND02D1: .6[.3] .43 U9.U4.U90.Z=sld_f 16.0[8.8] NI01D5: 1.9[.7] 3.79 U9.U72.U61.ZN 16.6[9.0] ND02D1: .6[.1] .30 U9.U72.U29.Z3N 18.4[9.7] DE24D1: 1.8[.7] .65 END U9.U72.U42.ZN 18.6[9.8] IN01D3: .2[.1] .63 ******************************************************************************** VLSItv> show delay start P13 end u9.sb_clk2 Rising Output: 4.6ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 2.1[1.4] LSTC00: 1.9[1.2] 3.33 U1113.ZN=sb_clk_- n_f 3.0[2.1] IN01D5: .9[.8] 4.52 END U9.U82.ZN 4.6[3.5] IN01D5: 1.3[1.3] 3.67 Falling Output: 4.3ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 5.21 THRU U1059.C .2[.2] PC6D00: .2[.2] 1.21 U638.IN=sb_clk_a- ux 1.4[.6] LSTC00: 1.2[.5] 3.33 U1113.ZN=sb_clk_- n_f 3.1[2.1] IN01D5: 1.7[1.5] 4.52 END U9.U82.ZN 4.3[3.0] IN01D5: 1.3[1.0] 3.67 ******************************************************************************** ******************************************************************************** 2. The pulse at the input of fsmchip->wrdav->davsel->davsync->U1 is at least one sb_clk wide and at most 2 sb_clks wide (is this what you meant?). 3. The delays from the pb_clk external pin (P26) to the pdata2_en signal in sbus_ctl is: to pspty (external pin P41) are: VLSItv> show delay start p26 end u9.u65.u9.zn Rising Output: 14.4ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P26 .0[.0] input .0[.0] 5.21 THRU U859.C .4[.4] PC6D00: .4[.4] 2.86 U860.IN 1.9[1.1] LSTC00: 1.4[.7] 1.45 U1137.ZN=pb_clk_- n_f 3.8[2.8] IN01D5: 1.9[1.7] 5.66 U9.U1.U38.ZN 5.2[4.0] IN01D5: 1.1[1.2] 2.95 U9.U1.U7.u26.Q 7.4[4.1] DFCTNB: 2.2[.1] .30 U9.U1.U41$2.Z=pc- _f[0] 9.1[4.6] NI01D5: 1.7[.5] 3.02 U9.U72.U54.U5.Z 10.8[4.9] MX41D1: 1.7[.2] .30 U9.U72.U54.U92.Z- =pdav_f 12.6[5.5] NI01D5: 1.8[.6] 3.43 U9.U1.U5.U2.u9.ZN 13.3[5.6] ND04D1: .7[.1] .45 U9.U1.U5.U2.u10.- ZN 13.8[5.9] IN01D1: .5[.3] .62 END U9.U65.u9.ZN 14.4[6.3] IN01D1: .6[.4] .34 Falling Output: 14.3ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P26 .0[.0] input .0[.0] 5.21 THRU U859.C .4[.4] PC6D00: .4[.4] 2.86 U860.IN 1.9[1.2] LSTC00: 1.4[.8] 1.45 U1137.ZN=pb_clk_- n_f 2.7[1.9] IN01D5: .8[.7] 5.66 U9.U1.U38.ZN 4.3[3.2] IN01D5: 1.1[1.3] 2.95 U9.U1.U7.u26.Q 7.4[3.3] DFCTNB: 3.2[.1] .30 U9.U1.U41$2.Z=pc- _f[0] 9.1[4.1] NI01D5: 1.7[.8] 3.02 U9.U72.U54.U5.Z 10.8[4.3] MX41D1: 1.7[.2] .30 U9.U72.U54.U92.Z- =pdav_f 12.5[5.3] NI01D5: 1.7[1.0] 3.43 U9.U1.U5.U2.u9.ZN 12.9[5.4] ND04D1: .4[.1] .45 U9.U1.U5.U2.u10.- ZN 14.0[6.2] IN01D1: 1.1[.8] .62 END U9.U65.u9.ZN 14.3[6.3] IN01D1: .3[.1] .34 ******************************************************************************** The propagation from the pdata2_en signal in sbus_ctl to pspty (external pin P41) is: VLSItv> show delay start u9.u65.u9.zn end P41 Rising Output: 7.7ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START U9.U65.u9.ZN .0[.0] input .0[.0] .34 THRU U9.U65.u10.ZN .8[.2] ND04D1: .8[.2] .44 U9.U105.Z=pspty_f 2.2[.9] NI01D5: 1.4[.7] 2.45 U413.Z 4.3[1.9] MX41D1: 2.1[1.0] 1.14 END U1239.PAD=P41 7.7[3.0] PT6S13: 3.5[1.1] 40.00 Falling Output: 10.1ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START U9.U65.u9.ZN .0[.0] input .0[.0] .34 THRU U9.U65.u10.ZN .5[.1] ND04D1: .5[.1] .44 U9.U105.Z=pspty_f 2.1[.6] NI01D5: 1.6[.4] 2.45 U413.Z 4.6[1.6] MX41D1: 2.5[1.0] 1.14 END U1239.PAD=P41 10.1[3.6] PT6S13: 5.5[2.0] 40.00 Since P41 is not inverted w/respect to pdata2_en, the total delay is: r = 14.4 + 7.7 = 22.1 f = 14.3 + 10.1 = 24.4 ******************************************************************************** The delays from pspty (external pin p23) on dataregs to the ffs in din_sel are: VLSItv> show delay start p23 end u8.u1.u208.u67.u26.d Rising Output: 12.9ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P23 .0[.0] input .0[.0] 40.00 THRU U1107.C .1[.1] PC6O45: .1[.1] .59 U495.IN=N_DL_IN 1.0[.5] LSCC00: .9[.4] 2.33 U8.U15.u5.ZN 2.8[1.9] IN01D1: 1.7[1.5] 1.01 U8.U15.u18.ZN 3.3[2.2] NR02D1: .5[.3] .61 U8.U15.u19.ZN 4.3[3.0] IN01D1: 1.1[.8] .59 U8.U15.u9.ZN 4.9[3.1] OA02D1: .6[.1] .34 U8.U1.U100.Z 6.1[3.3] NI01D3: 1.1[.2] 1.03 U8.U1.U192.Z 8.3[3.8] OR03D1: 2.2[.5] .70 U8.U1.U208.U72.ZN 9.6[4.6] NR02D1: 1.4[.8] .38 U8.U1.U208.U67.U- 51.Z 10.8[5.2] NI01D3: 1.2[.6] 1.33 END U8.U1.U208.U67.U- 52.Z 12.9[5.3] MX41D1: 2.1[.1] .31 Falling Output: 12.9ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P23 .0[.0] input .0[.0] 40.00 THRU U1107.C .1[.1] PC6O45: .1[.1] .59 U495.IN=N_DL_IN .9[.6] LSCC00: .8[.6] 2.33 U8.U15.u5.ZN 1.7[1.2] IN01D1: .8[.6] 1.01 U8.U15.u18.ZN 3.7[2.7] NR02D1: 2.1[1.5] .61 U8.U15.u19.ZN 4.2[3.0] IN01D1: .5[.3] .59 U8.U15.u9.ZN 7.2[3.7] OA02D1: 2.9[.7] .34 U8.U1.U100.Z 8.2[4.2] NI01D3: 1.0[.4] 1.03 U8.U1.U192.Z 9.7[5.1] OR03D1: 1.5[1.0] .70 U8.U1.U208.U72.ZN 10.1[5.3] NR02D1: .4[.2] .38 U8.U1.U208.U67.U- 51.Z 11.3[5.6] NI01D3: 1.2[.3] 1.33 END U8.U1.U208.U67.U- 52.Z 12.9[5.7] MX41D1: 1.6[.1] .31 ******************************************************************************** VLSItv> show delay start p23 end u8.u1.u208.u67.u21.d Rising Output: 13.9ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P23 .0[.0] input .0[.0] 40.00 THRU U1107.C .1[.1] PC6O45: .1[.1] .59 U495.IN=N_DL_IN .9[.6] LSCC00: .8[.6] 2.33 U8.U15.u5.ZN 1.7[1.2] IN01D1: .8[.6] 1.01 U8.U15.u18.ZN 3.7[2.7] NR02D1: 2.1[1.5] .61 U8.U15.u19.ZN 4.2[3.0] IN01D1: .5[.3] .59 U8.U15.u20.ZN 6.6[4.5] NR03D1: 2.4[1.5] .51 U8.U1.U139.ZN 7.0[4.7] ND02D1: .4[.2] .29 U8.U1.U140.ZN 9.3[6.6] ND02D1: 2.3[2.0] 1.31 U8.U1.U208.U93.Z 11.5[8.0] AN03D1: 2.3[1.3] .94 U8.U1.U208.U67.U- 39.Z 12.7[8.5] AN02D1: 1.2[.5] .45 END U8.U1.U208.U67.U- 55.Z 13.9[8.7] MX41D1: 1.2[.1] .30 Falling Output: 13.9ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P23 .0[.0] input .0[.0] 40.00 THRU U1107.C .1[.1] PC6O45: .1[.1] .59 U495.IN=N_DL_IN 1.0[.5] LSCC00: .9[.4] 2.33 U8.U15.u5.ZN 2.8[1.9] IN01D1: 1.7[1.5] 1.01 U8.U15.u18.ZN 3.3[2.2] NR02D1: .5[.3] .61 U8.U15.u19.ZN 4.3[3.0] IN01D1: 1.1[.8] .59 U8.U15.u20.ZN 4.8[3.2] NR03D1: .4[.2] .51 U8.U1.U139.ZN 5.4[3.5] ND02D1: .7[.3] .29 U8.U1.U140.ZN 6.9[4.7] ND02D1: 1.5[1.3] 1.31 U8.U1.U208.U93.Z 8.3[5.3] AN03D1: 2.3[.6] .94 U8.U1.U208.U67.U- 39.Z 9.2[5.5] AN02D1: 1.2[.2] .45 END U8.U1.U208.U67.U- 55.Z 13.9[5.7] MX41D1: 4.7[.1] .30 ******************************************************************************** The delays from pin P26 to the clock input of the ffs in din_sel are: VLSItv> show delay start p26 end u8.u1.u206.z Rising Output: 5.8ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P26 .0[.0] input .0[.0] 100.00 THRU U859.C .4[.4] PC6D00: .4[.4] 2.86 U860.IN 1.9[1.2] LSTC00: 1.4[.8] 1.45 U863.Z=pb_clk_d 3.7[2.3] NI01D5: 1.9[1.1] 3.81 END U8.U1.U206.Z 5.8[3.6] NI01D5: 1.8[1.3] 3.47 Falling Output: 6.1ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P26 .0[.0] input .0[.0] 100.00 THRU U859.C .4[.4] PC6D00: .4[.4] 2.86 U860.IN 1.9[1.1] LSTC00: 1.4[.7] 1.45 U863.Z=pb_clk_d 3.7[1.8] NI01D5: 1.9[.7] 3.81 END U8.U1.U206.Z 6.1[2.9] NI01D5: 1.8[1.2] 3.47 4. The pulse at the input of drdsync->u11 is one sb_clk wide. The pulse at the input of drdsync->u15 is at least one sb_clk and at most 2 sb_clks wide. 5. The pulse at the input of ps_sync->u1 is one pb_clk wide. The pulse at the input of ps_sync->u11 is at least one pb_clk and at most 2 pb_clks wide.