Bug and problem list

- on pctlfsm, eofout depends on inputs done and op_done, which
  come from another chip--timing problem.

- there is an extra clock just before iosel goes high because
  it takes one extra cycle to detect op_done since the ffs were
  added in dataregs to alleviate timing problems.

- on the CAM chip, lsout comes from data_valid (on reg_len_dcd),
  which depends on dlen_ld_n (generated on opc_reg), which depends
  on iosel--check with Tom to see if this propagation path can occur.

- on prdfsm, eofout depends on done--timing problem.

- on pwrfsm, eofout depends on pdav and done--timing problems.

- in node logic, lsout and rsout depend on rden_n (dwg. node_sel)
  which depends on ioin (rwfsm_p)--timing problem.

- in node logic, lsout and rsout depend on f (dwg. node_sel),
  which depends on rstnd_n (nodefsm_p), which depends on ioin
  (rwfsm_p)--timing problem.  This also applies to the e input
  to node_sel; it's controlled by rstnd_n (node_inv).

- in node logic, ioout and dout depend on the full output from
  nodefsm_p, whick depends on ioin--timing problem.

- on dataregs, drparam_n, which drives sb_siz, comes from the
  fsmchip--possible timing problem.

- on dataregs, sdr_n, which drives the sbus data, comes from the
  fsmchip--possible timing problem.


5/26/92
  Ground u9.u1.u11.u14.a1