Ctlsvchip Clock Tree		1/30/92

				sb_clk		pb_clk
ctlsvchip
  clrsync					  1 (1)
  csvsel
  control
    controlreg			 16 (3)
    				 16 (2)
    				 10 (1)
      upctr16			 16 (4)
        upctr4 = 4 (x4)
    dnct_ctl					  1 (2)
    dnctr16_a
      dnctr4_a = 4 (x3)				 12 (2)
      dnctr4_b = 4 (x1)				  4 (2)
    opcode_reg					  9 (1) (5 dummy)
  slave
    wait_stat			  4 (1) (2d)	  3 (3) (1 dummy)
      xsync (dup)		  2 (1)
    slavereg			 16 (5)
      ptr_reg			 16 (6)
      ptr_reg			 16 (7)
      ptr_reg			 16 (8)
				  1 (11)
      sb_va_gen			  1 (11)				
      bus16_2
      sync_gen			 16 (9)		 16 (4)
				 16 (10)	 16 (5)
				  1 (11)	  1 (3)
        xsync					  2 (3)
        sync_fsm_p				  6 (3)
        sync_encode				  6 (3)
        sync_ctr = 16 (x2)
          dnctr8 (x2)
            dnctr4 = 4 (x2)
    eosi_dcd			  9 (13) (7d)	  5 (1)
    hnp_ctl			  1 (13)
      hnp_fsm_p			  6 (13)
    xsync			  2 (11)
    reg_1
      intreg			 14 (12) (2d)
        int_cond		  5 (11)
          ci_sync		  2 (11)
      cmd_reg			  4 (11)	  2 (1)
  				---		---
  				196		 81
Loading:

s1 = 16
s2 = 16
s3 = 16
s4 = 16
s5 = 16
s6 = 16
s7 = 16
s8 = 16
s9 = 16
s10 = 16
s11 = 16
s12 = 16
s13 = 16 (5 dummy)

p1 = 17 (5 dummy)
p2 = 17
p3 = 17 (2 dummy)
p4 = 16
p5 = 17

/im/faust/txt/c_clk.txt