Dataregs Clock Tree		2/4/92

				sb_clk		pb_clk

dataregs
  fsm_dec_p
  sb_drv			  1 (5)
  sv_oncircuit			  1 (5)
  clrsync (dup)					  1 (6)
  dataout			 16 (6)
    ldsel
    dout_sel			  1 (5)
      upctr2_a			  2 (5)
    doutreg (reg 7)				 16 (1)
    doutreg (reg 6)				 16 (2)
    doutreg (reg 5)				 16 (3)
    doutreg (reg 4)				 16 (4)
  datain					 13 (6) (5d)
    dinreg (u87$1-16)		 64 (1-4)
    din_sel					  2 (6)
      upctr2_a					  2 (6)
    din_ctl					  1 (5)
    ptygen8			 		  1 (5)
      pty_p (u1$1-8)		 		 16 (5)
  				---		---
  				 85		 98
Loading:

s1 = 16
s2 = 16
s3 = 16
s4 = 16
s5 = 16 (11 dummy loads)
s6 = 16

p1 = 16
p2 = 16
p3 = 16
p4 = 16
p5 = 18
p6 = 17 (5 dummy loads)

/im/faust/txt/d_clk.txt