Norm/Ken,

  I modified the Verilog code in my directory (use dcam
to run) so that the "vector eater" stops the *pbus*
clock after it goes high.  Ken, the clock assignment
in chip1.edf.v[.b] needs to be slightly different:

     clk=p25 | !system.U5.vector_enable;

The tests I ran worked.  Please let me know if there
are any more problems.

                    Doug