Norm,

The reason that the interface does a burst per bit in mode 0
transfers is that it does a bus request (for a new burst) as
soon as the current burst is complete.  Because of the holdups,
the next burst results in a "spill", i.e., an attempt to load
the data registers before their contents have been accepted by
the cam chip.  The interface then repeats the bus request until
no spill occurs.  The timing of the holdups results in one burst
per bit transferred.  I agree that this is a lot, but it's
because the interface is optimized for large, no holdup transfers.

                                 Doug