- TAR reg 10 = broadcast 11 = LUT select (16 bit counter) - select on glue is effective only if the selected chip is not driving the glue line which select it. 6/12/90 called Cadence re DFF primitive which is found in their VTI library. DFF and others are defined in the file /im/verilog/vlsi/vlsi_1.0u/udp/vlsi_udps.vmd (spoke to Ray Salemi). - vtiplot creates a vti shell file which can plot all files after the named file (but not including the named file). - any bus error while writing the scan start should prevent the scan from starting. - for the interface chips, assign the clock tree to a signal which doesn't toggle often (use the reset line) to save power. Connect the clock tree to the same pin as the interface reset pins. Use the config pins to select the source of the reset for all chips (from either the clock tree or the CAM reset pin). - Does the graphics card support burst mode? - when the CAM chip sends invalid data, the data must be all 0's - Pbus protocol for r/w line: if iosel is low for 1 valid bit: that bit is parity and the operation is write reg 0 if iosel is low for 2 valid bits: the first bit is parity. if the second bit is 0, the operation is read reg 0 if the second bit is 1, the operation is write reg 1 - parity will be ignored until the parity interrupt is enabled - 9/21/90 make sure that if an Sbus error occurs in the middle of a CAM read that the read is completed so that the shift registers will not be scrambled. - 10/9/90 we would like to implement the data in registers more like a FIFO so that there is less chance of a spill occurring. David will try to mark up drawings to implement this while he is in Trinidad. - 11/2/90 modify the interface to do error acknowledgements properly - 11/2/90 in sequential read mode, each module, when selected to read, will add one (even) parity bit to the end of its data, so that the net parity of all data is zero. Therefore, the overall parity will be the parity of the opcode. Since all modules listen to the opcode, all modules will check parity and act accordingly. The interface treats the extra parity bits as data; the host can check this parity "manually", if desired. - 11/6/90 Note that in the Sparcstation I, PA [27:25] are driven but unusable (page 118 in the Sbus manual) - 11/8/90 donesync has bug; make sure that the clear input overrides the edge detector on the j input of the jkff. VLSI meeting 10/23/90 - add power & ground pads to top level schematic - don't use dfctnn flip-flops (non-buffered) - fix the synchronous clear problem - supersynchronous vectors are at 1 MHz - outputs must be strobed at time 980 - 6 timing generators - don't clock anything at time 0 - vector utility converts tabular input to [vif] - use predcap file (capacitance predictor) - at signoff need screen report & - use profault to check node coverage Verilog system simulation notes - add conditional looping in system.v - add sbmem dump to file at end of simulation with specifiable start and length; use a second file as semaphore; write 1 when done, 0 will be written by control program when OK to loop 2nd line will be start adddress to dump 3rd line will be length in bytes (could be 0) format of dump file: like MSDOS debugger repeat header every 32 lines use plusarg +loop to specify looping mode allow different configs of cam chips 12/4/90 Notes on integrating cam.edf.v into system.v: - in cam.edf.v, change "vss" to "1'b0" - in cam.edf.v, change "vdd" to "1'b1" 12/11/90 PBus left status out protocol (CAM to interface): write: 0 = ready to accept data 1 = not ready read: 0 = invalid data 1 = valid data left status in protocol (interface to CAM): write: 0 = valid data 1 = invalid data read: 0 = ready for data 1 = not ready for data 12/11/90 path for vss, vdd symbols = cmosch000x/support/Logic Assistant 1/3/91 Screensaver doesn't appear to work properly on im4 under Suntools. It's turned on by /etc/rc.local 1/3/91 Add support for 64 word burst modes? 1/10/91 Add interrupt enable FF to ctlsvchip (bit 29 of slave control word) to prevent Unix from crashing if interrupt occurs before board is "attached". slave reg contents at beginning of memory--don't write if 0 Think of another finish condition. Host wait bit and host error bits--make visible Don't clear interrupts when status is read! 1/17/91 Add host error status; make clearable (called reset int wait) - bit 4 If enough pins, add an address line to ctlsvchip and make the status register a separate address. Add Sparc 2 bit to reset address (1) Add new status bits plus control flags to address (4) Here replace eos bit with "scan active & eos". Here replace hw bit with "hw & waiting". Read transfer address at address 5 Read transfer length at address 6 Read link at address 7 1/22/91 unix notes (from td) jobs displays stopped jobs w/numbers kill %1 will kill stopped job #1 fg %1 will restart stopped job #1 1/24/91 Interface problem: In write mode, the interface sctlfsm will request an extra burst of data if "done" has not been set. This could be eliminated by providing an extra done status to the sctlfsm when the pbus count has 8 or fewer words to go. This information could be added to the existing "done" status by using one transition to indicate "8 or less to go", and the other transition to indicate "done". 1/30/91 Had a problem involving the system loop mode today. I was running Verilog on im7 and step on im4, and occasionally Verilog would read a "1" as the first character in the file done.v while vi (running on im4) showed done.v to contain all 0's. This didn't happen if I ran Verilog and step both on im4. 1/31/91 In sctlfsm, differentiate between a CAM interrupt and other error conditions (Sbus interrupt or CAM timeout), and allow the current transfer to complete if the error is a CAM interrupt. 2/5/91 VLSI-- we get one vector per gate; more costs extra The chip can have only one clock tree. Using 5x buffer to drive up to 15 clock loads. Need number of simultaneous switching outputs. Use 1000 ns cycle; don't change any input at test cycle boundary. Change inputs only at 100 ns boundaries. 2/5/91 Running VLSI screen: type: utility screen read [nls] array vgt300077 screen prerouteinfo freq 7 sort 7 (answer no to sort in ascending order question) write 2/7/91 What should the state machines do when an error is encountered? Sbus error acknowledgment: sctlfsm should go to waitst state (abort). scamwrfsm should go to idle state (abort). scamrdfsm should go to start state (abort). pctlfsm should go to pidle state (abort) if write, continue normally if read. pwrfsm should go to wrwait state (abort). prdfsm should continue but not wait for pdrd signal in pdrd1 state. Sbus Late error: sctlfsm should complete any transfer in progress, then go to waitst state. scamwrfsm should complete any transfer in progress, then go to idle state. scamrdfsm should complete any transfer in progress, then go to start state. pctlfsm should go to pidle state (abort) if write, continue normally if read. pwrfsm should go to wrwait state (abort). prdfsm should continue but not wait for pdrd signal in pdrd1 state. Cam timeout error: sctlfsm should complete any transfer in progress, then go to waitst state. scamwrfsm should complete any transfer in progress, then go to idle state. scamrdfsm should complete any transfer in progress, then go to start state. pctlfsm should go to pidle state (abort). pwrfsm should go to wrwait state (abort). prdfsm should go to rdwait state (abort). Cam interrupt: sctlfsm should go to waitst state after the current instruction is completed. scamwrfsm should operate normally. scamrdfsm should operate normally. all pfsms should operate normally. 2/12/91 Should we have a separate status bit for an Sbus error that happened during the translation phase? 2/18/91 Timed cama systema" with graphics wave window open and closed. The times (including compile/link): Closed = 3:13 Open = 7:22 The compile/link time is :45, so the simulation times are 193-45=148 and 442-45=397. For this case, leaving the window open increases simulation time by 397-148=249 seconds, or 160 percent! 2/27/91 In pctlfsm state xmtrd, the unlatched output drop (drive opcode) depends on the eofin input--this is bad. - check for other similar situations (on drpty and pdrdata) - the signals drop, drpty, and pdrdata go off chip, onto the dataregs chip, through gates, and then to tristate enables. We need to fix it (if possible) so the output enable gets clocked into a ff on the dataregs chip. Watch out for similar situations. 2/27/91 In step program, type 0 0 step-init at the beginning. 3/4/91 system4.v takes about 10 minutes to compile & link on im9. 3/7/91 the burst counter is implemented wrong; fix it by eliminating bits 2-0 from the load and using them to sense the "one" condition. 3/11/91 fix chip1.edf.v by doing the following: - add a timeset statement at the beginning - comment out the ptnc12 clock buffer and add the statement: assign clk = p25; 3/12/91 write 10 (decimal) to the multipurpose function select to make the pin be lsout. 3/12/91 Sbus Verilog model has a bug (concerning error acks??) 3/12/91 Remember to replace the pads for the multipurpose pins with pulled up pads after simulation! 3/14/91 multipurpose pin connections chip0 - status (reset (module 0) input/interrupt out), lsout chip1 - iosel out, rsout chip2 - cs0, we0 chip3 - cs1, we1 alternate assignments chip1 - enable_bus_in_n (toward host), enable_bus_out_n (away from host) alternate alternate assignments chip1 - bus direction (0 = toward host), enable_bus_n multipurpose pins: all multipurpose pins wake up as inputs Multipurpose pin defaults for 8 chip model (all signals are outputs except as noted): mafs mbfs status status-input lsout rsout cs0 we0 cs1 we1 data-direction data-enable display-active site-valid sync iosel scan scan-input reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 3/20/91 Make schematics and print out iboard.v, ctlsvtop.v, etc. for Ken. 3/21/91 Make up a system with two single bit modules. 4/2/91 The way to make Verilog print out the data structure size is by using the $stop(2) statement. 4/2/91 In a cam box, we need to have bidirectional buffers for pbus data whose direction controls come from a multipurpose pin. The direction control for the data back to the interface will be the OR of eight modules so that reads will work. 4/4/91 Add a bd4 to the late error input on fsmtop to get rid of x's. 4/8/91 Need a ff which gates off cam reset until the cam chip has been given a reset pulse. 4/9/91 How to detect when the interface is halted after issuing a halt command: - schedule a noop, host wait instruction - wait for new list interrupt; when this happens, the noop instruction burst will be done and the interface will be waiting for a host next pointer. 4/11/91 The sync signal is encoded as follows (the bit on the left is sent first): 1001 = HMON (Monitor horizontal sync start; 1 --> 0 transition) 1010 = VMON (Monitor vertical sync start; 1 --> 0 transition) 1100 = HCAM (CAM horizontal sync start; 0 --> 1 transition) 1111 = VCAM (CAM vertical sync start; 0 --> 1 transition) 4/17/91 Modify reset to come from the fsmchip, which will wait a certain number of clocks after a bus grant (if there was a request) and then give a reset to all interface chips. 4/18/91 Halted status should not include waiting for host next pointer to be written. 4/23/91 Check sb_irq spec--there are seven levels (not one per slot). 4/23/91 Use pullups & pulldowns on "hard-wired" pins? 4/23/91 Segmentation faults in verilog have occurred for the following reasons: - wrong number of module port connections - not enough signals to satisfy a $display string (i.e., too many %b's or %h's). 4/24/91 Change reset circuit so that svfsm and sbugfixfsm don't get reset by the soft interface reset. Add status to reg1 which indicates "reset pending". This allows software to know when the reset has occurred. 4/24/91 On the cam chip, int_out and int_in should be inverted. I fixed this in /im/cam8/vsim/df/chip1.edf.v, but nowhere else. 4/25/91 scan-io write Tom will be in around lunch time. 4/25/91 sync circuit--sync interrupt is occurring. 4/30/91 To test error acknowledge: put the simulation into interactive mode just before the transfer where you want the error ack. Set the integer U5.U1.do_error=1. Continue the simulation. The simulation will enter interactive mode just before it does the transfer; now set the variables ack_code, ack_interval, error_delay, and late_error as desired. ack_code: use 1 for error ack ack_interval: number of cycles between acks error_delay: which ack is the error ack late_error: set to 1 for late error The values you enter will be good for the immediate burst only. They will be reset to normal after this burst is done. 4/30/91 The PROM on the interface board is 8K x 8? We will allow for a 64K byte PROM address space and move the registers to just above that, i.e., use sb_pa [16] for the register select bit. 4/30/91 National DS3695(DS36950?) is the differential transceiver which Sun uses for its Sbus expansion box. 5/8/91 in qsim, type: option profault on read or load netlist node <$$dummyname> (dummy name for profault clock) set clock (profault) dummyname where is half the simulation clock frequency (samples on both edges). strobe load [sim] this generates an output file (KC doesn't remember name). 5/8/91 Use the [Unix] wc (word count) command to count lines, words, and characters in a file. 5/8/91 Patches to chip.edf.v: assign sb_clk_c = p13; assign pb_clk_c = p26; assign sb_clk_f = p13; assign pb_clk_f = p26; assign sb_clk_d = p13; assign pb_clk_d = p26; - replace pt6o11 with bd4 - replace pt6o12 with bd4 - replace pt6o42 with bd4 5/9/91 Errors in pinout.txt: - param_dr_f should be param_dr_n_f (pin 49) - suspend should be suspend_f (pin 52) - sb_reset_n_f is an input, not an output (pin 53) 5/15/91 How to run vlsi vector checker (in vlsishell): utility check input [trc]ctlsv netlist [nls]chip itg [itg]ctlsv (seems to be mandatory) duration 1000 source vlsiqsim output ctlsv create quit quit 5/21/91 KC at VTI says for supersynchronous vectors: - use an .itg file to specify timesets to the checker. - use dynamic trace mode in qsim. On the subject of clock buffers and distribution: - you can't generally use more than one clock input buffer per chip. The clock buffer makes the router try to generate a spline distribution. - for the secondary clock(s), use a tree of ni01d5 if delay is not too critical, or in01d5's if delay is more critical. Each buffer can drive about 15 loads. 5/28/91 The display signal will be bussed within the same box but will not be tied together between boxes. It will be pulled down by the ninth board in the box, which will have video circuitry and possibly a video connector (per TT). 5/29/91 - Change sys12a.v to implement enable/direction pin functions rather than enable/enable. - Add ff to status logic in all sys.v files. - Have Tom D. hand check operation of status OR function. - Add delay to sram assignment statements 5/30/91 In the middle of doing pb_clk tree on ctlsvchip. 6/4/91 Doing sb_clk tree on fsmchip/sbus_ctl. 6/5/91 Check pinout.phys against my list. 6/6/91 on 8 chip module: tie status-input low. tie scan to scan-input. 6/6/91 model with 4 two chip modules, 2 modules at each level of bus. 6/6/91 To print a file in landscape format, type: enscript -1r 6/6/91 How to run profault report program in vlsishell: utility fault (select simulator type ProFault when prompted) read [txt]netlist_pfs write [txt]netlist_pfs_summary Use the SHOW command to display coverage of specific modules: show u1.u10 6/6/91 Design review Thursday June 13. 6/6/91 Fix sync connections on models with >1 bus levels. 6/11/91 3:00 pm KC @VLSI He says there is a bug in profault which makes if fail with muxed flipflops (mfctnb). There is a way to somehow make a substitution of a mux and ff for each mfctnb in the netlist; he will call back with details. 6/12/91 To run a program while remotely logged in and not have it die when you log off, use the 'nohup' command before the desired program name. This will run the program in the background. Remember to kill the job off later. 6/12/91 KC @VLSI -- his Wilmington number is 508-658-7686 workaround for profault bug w/mfctnb create muxed ff w/same pins as mfctnb "mymfctnb" make switch file ,, "switch utility" software bug list - he will call the guys at Compass and have them send one. if it says can't find netlist, call KC back. edit switch file and replace last asterisk on the line with either "working" or library name. unknown clock problem ok as long as outputs are not affected. do clock tree nodes need a weight? how much? put weights at end of tree, try 8. how to make a switch file: - call up a "switch" window - click left button on "edit" at bottom of window - click left button on "add" - click middle button on "source type" until it says "nls" - click middle button on "destination type" until it says "nls" - click middle button on "source" and enter the cell name you want to replace, e.g., "mfctnb". - click middle button on "destination" and enter the cell name you want to substitute for the source, e.g., "mfctnb_a". - click on "save" and type filename. - in qsim, say "set switch " before loading netlist 6/13/91 Design review--Bill Dally, Rick Lethin Logic Automation has Verilog DRAM models we could use. VTI may have Spice models for its output buffers. Recommends specifying 75 ohm impedance on PCB traces. Recommends using ECL buffers--they act as wire-or, so direction & enable controls aren't needed (just care in leaving the input to the ECL buffer high when not used). He thinks the glue cables should have more ground pins than signal pins (how many more??). He favors clocking scheme where each box's clock goes over a matched coax cable and is tweaked for minimum skew. Seems to like Norm's scheme w/Gazelle phase locked loop. 10k hours mbtf for a chip 6/17/91 Can't get the switch option of qsim to work. Tried substituting "working", "chip", and "interface" for the last asterisk in mfctnb_a.swt, but I get the identical (wrong) result when I run faultReport. 6/17/91 change all pins with 4 ma drivers to cmos logic levels and reassign sbus pins to 2 ma driver pins (4 total). Make sure that all inputs from the bus have cmos levels. 6/17/91 don't forget to read mail from Tom. 6/18/91 delays for pc6o12 (cmos 4 ma driver, pullup) and pc6042 (cmos 4 ma driver, no pullup) pt6011 (ttl 2 ma driver, pullup) pt6041 (ttl 2 ma driver, no pullup) Load 5 pf 10 pf 20 pf pc6o12 i->pad (rise) 2.85 3.76 5.59 (fall) 3.09 3.72 4.99 pc6o42 i->pad (rise) 2.86 3.77 5.60 (fall) 3.01 3.60 4.79 pt6o11 i->pad (rise) 2.90 3.86 5.78 (fall) 5.92 7.19 9.74 pt6o41 i->pad (rise) 2.93 3.90 5.84 (fall) 5.68 6.87 9.25 6/18/91 KC @ VLSI - need 3x clock w/switch file buffer from KC. this stuff is fixed in new version. - switch file isn't working for profault stuff. he will send new mfctnb model w/clock stuff. - can we drive a bidirect input with a signal of pullup strength for test vector purposes? - suggests using new version of software to fix many problems - he says the cmos and ttl output buffers are really identical so we can drive VLSI cmos input buffers with VLSI ttl output buffers. 6/18/91 uuencode filename1 filename2 converts a binary file to ascii format so it can be sent via email. filename1 is the source filename and filename2 is the name that file is to be given at the destination. nslookup is used to find email addresses. 6/20/91 KC @ VLSI in netlist, try (sim) [nls]name to fix hierarchical netlist problem 6/24/91 1:15 Spoke to Jim Veneria (sp?) @VLSI--he says he forgot to call KC on Friday but will call him immediately to start getting the edf output problem resolved. 6/24/91 2:30 Found that the edf problem is caused by the pt6c14 clock input buffer. 6/27/91 The fault coverage on the svfsm is lower than expected, especially on U10 (nd03d1), whose output is ackdr_n. This is just a decode of several different states, so if the fsm is completely exercised there should be excellent coverage. Need to check this out further. 7/1/91 on cammod8.v, connect scan to scan-input site-valid is open 7/1/91 Created fanout.v to demonstrate that Verilog doesn't change gate delays depending on fanout. 7/2/91 Logic Automation Verilog models are TC514402 (1M x 4 dram, p. 359), and MCM6208-20 or -25 (64k x 4 SRAM, p. 258) or MCM6209-15, -20 or -25 (64k x 4 SRAM, p. 555). The models are in /usr/lai_vlog/lib The verilog command line or the command file should have the following line: -v /im/verilog/lai_mods.v 7/3/91 I changed chip3 to have a pullup on p4 to see if this fixes the problems with the fsmchip test vectors. The original chip3 was saved under chip3_bak.la. 7/23/91 There are a problems when a timeout occurs. First, the prdfsm sees a timeout pulse immediately and goes to the rdwait state, but the pctlfsm sees the timeout only after it causes the "error" signal to be asserted; until then, the "ok" signal is asserted, causing the prdfsm to start up again! Changed prdfsm to enter an "errwait" state which waits for ok to be deasserted, then enters the rdwait state. The second problem is that the software clears exception status before reading the interrupt word. Since the hnpfsm detects the level (not the edge) of tmcmint, it immediately returns to the exception state after the "clear exception," because tmcmint has not gone away. We can fix by changing hardware or software. 7/25/91 How to use the timing verifier: in vlsishell: tv load [nls]netname show critical 1 nodename 7/25/91 KC at VLSI: - vectors can be in up to 9 separately runnable blocks. - he will check the dataregs test vectors on the Mach. 7/29/91 Couldn't reproduce problem with /im/cam8/vsim/verify/exp/ecsr.map.old.exp (see bug-report from nhm dated 7/29/91) using the release directory (release.july7). The step program dumped control back to Unix before any cam reads were done. The simulation ran with release.july25. 7/29/91 Spoke with Kim Owen at Logic Automation regarding problem with timescale differences between our Verilog code and the memory models we are using. I suggested that the solution might be to use a defparam statement to force the model's TIMESCALE parameter to a value of 1, and he seemed to agree, but said he would check on it and call back. We later found in the Logic Automation User's Manual that the file with the models in it (lai_mods.v) should have a `timescale statement inserted at the top as follows: `timescale 100 ps / 100 ps This fixes the problem without the need for a defparam. 8/5/91 Discovered that, in vlsiwave, to use tabular input IN HEX FORMAT, there must NOT be a space between a bus name and the left bracket that starts the bit specification. This applies to both the PINORDER list and the GETTABLE statement. 8/5/91 Re the bug report using /im/cam8/vsim/verify/exp/select.read.exp (unexpected bus parity interrupt when reading the select register), the problem is occurring because lsout is being asserted by cam chips 00 and 10 at different times, causing confusion as to which bits are valid. 8/7/91 In VLSI window, use oscplot program to display output from qsim. Set the format to (dynamic, tabular) and the oscplot program will be able to read in the .trc file directly to generate waveforms. Alternate way to use oscplot: In the .sim file, the watch command must use the (display) option to generate the .wfd and .wft waveform files. Also, there must be a wave command to specify the filename. 8/8/91 oscplot gets fatal errors often! The worst combination seems to be defining a time grid and then select BB (bounding box). This frequently generates a Mainsail arithmetic error. 8/8/91 Differences between chip3 and chip (the real one): - the cam circuitry is eliminated - a normal input buffer is substituted for the ptnc14 clock buffer - two cam signals are tied to ground: N_DOUT DOE_N 8/8/91 Tom Donnely's email address: .wrl!vlsisj!saab!tomd 8/26/91 Logic Automation support hotline number (Oregon): 503-690-6920 8/27/91 In qsim, use the set simparms command to set the default transistor delay to speed up the effect of pullup and pulldown transistors, e.g., set simparms transistorDelay 10 Note that this command must be given before the netlist is loaded! See the file /im/faust/bin/svec for an example 8/28/91 In the vti timing verifier (tv), use the "set option noblast" command to make the verifier stop at storage elements. Otherwise it will find outrageously long paths that you are not interested in. Also, use the "set padslimit n" command to eliminate pads going off and on the chip several times. If measuring the delay from an input pin to an output pin, use "set padslimit 2". 9/3/91 Note: two pins on the lsb ctlsvchip can be eliminated by duplicating the rd and immed bits in the lower half of the flags control word. 9/4/91 The VTI logic synthesizer can't be trusted to give a usable result in some cases. My problem was that eofin had to propagate through prdfsm, through one ctlsvchip, and set up in the other ctlsvchip. The solution was to eliminate eofin as a component of the signal (a counter enable) that goes to the ctlsvchips, so I redefined the state machine to do this. The resulting schematic had the correct static function, but there was a race condition which could cause a glitch if eofin transitioned from low to high. A simulation did not produce a glitch because the race happened to be resolved innocuously in the Verilog model; however, adding delay to one of the logic paths did indeed induce a glitch. So be cautious with the synthesizer! 9/4/91 In VTI, to change a [pcl] file, just place it on a schematic; a box will pop up to let you change its parameters. 9/4/91 run "dcam sys1x" to check mods to chip3. 9/17/91 the dc program is a "desk calculator" 9/19/91 telnet sun-bear guest forftp ftp im4 cd /im/cam8/plots get filename lpr -s -Pbear-mountain filename 9/23/91 stuff to do: - hand check chip.la - done 9/23/91 - revise test vectors - 9/25/91: all nodes toggled - check propagation on all outputs - find max operating frequency - 9/24/91: works @35 ns cycle, fails @ 33 ns (register test suite) - find worst setup time on inputs - check with fast and slow pclk 9/25/91 fix X's on ack in fsmchip vectors at time 792980. 9/30/91 In the vlsi logic assistant, use a "bus shorter" module to tie several bus lines together; this module is found in the LOGIC ASSISTANT category of the cmosch000x library. 9/30/91 timing problem: the propagation of sb_va_en is 12.4 (from clock) on fsmchip, and 12.0 (to sb_d output) on ctlsvchip, for a total of 24.4--this is too slow for the 25 mhz sbus (20 required). 10/9/91 Make a model with 6 *full* chip models and run register test. 10/10/91 Would like to improve timing of op_data--check pctlfsm for feasibility. done, 10/15/91 10/15/91 Add random waits on ack to verilog sbus model. 10/16/91 check timing on node logic in cam chip. 10/21/91 continue with slow pb_clock testing. 10/23/91 in qsim use load [sim]pred077 to load predcap file, 10/28/91 finish working on chip.la 10/31/91 adding latch to output of dataout.la; finish select logic. 11/4/91 patched fsmchip.edf.v in release directory to fix a cam mode 0 problem caused by multiple spill states in swrfsm. The timing on pdata2_en had been changed but the dout_stat module which uses this signal had not been modified to accommodate the change. 11/12/91 make models to test high bits of interface bus 11/12/91 using the 'cat' command, the hyphen ('-') indicates console input. 11/21/91 does the pbus work with holdups?? 11/27/91 fix clock trees on fsmchip and dataregs 12/2/91 - equivalent to LCHK doesn't exist use watch *.d to look at all ff inputs. - clock tree generator not planned - suggests we make clock tree a bus (for convenience only-- doesn't affect router). 12/3/91 vtest dcam1 regs ends at time 3891750 12/5/91 make long reset 128 clocks 12/5/91 On top level drawing, renamed the following clocks: sb_clk_d -> sb_clk_n_d sb_clk_f -> sb_clk_n_f pb_clk_f -> pb_clk_n_f 12/5/91 /sim/nhm/new/x2.4.error.exp generates an interface error because of long holdups during opcode transmission. The problem appears to be that pdav is getting cleared by the pctlfsm from the previous data transfer. 12/9/91 kill Norm's stuff by killing script 12/10/91 Still have untoggled nodes in fsmchip test vectors. The problem doesn't appear in the Verilog simulation. 12/18/91 Looks like there may be a problem with byte mode reads. Check the debug output in vlog. 12/19/91 Close an xwindow by holding meta key and clicking left mouse button. 12/30/91 To mount theory server, log in as root, then do: mount -h theory (this doesn't work--h is umount option only) or mount -a -o remount 12/31/91 upctr16 in controlregs needs faster incout signal. Add a "ones" output to upctr4. 1/2/92 tcam4b failed after approx 13k characters written to the flog file. Use tstep with /sim/nhm/m1.1.exp. 1/2/92 Modify the model to monitor the cam status line for x's and stop and display a message if it becomes x's. 1/6/92 /sim/nhm/x3.8.ctv.exp is Norm's new exerciser for CAM (and the interface). 1/6/92 Idea for reducing cam simulation time: eliminate extra sbus bursts. Turn off clock to CAM when interface is busy and cam is waiting. 1/8/92 Timing concerns on ctlsvchip: p17, 18, 19 (sc[2:0])--up to 24.6 ns setup time (15.9--ok) p12 (hnp_sel_out)--22.4 ns propagation (14.2 setup) (ok) p20 (sld)--27.0 setup (10.5--ok) p24 (sync_out)--23.8 propagation (22.7) p45 (hstop)--25.9 prop (18.0--ok) (17.7 setup) p46 (od_ri)--28.7 prop p49 (incout)--34 prop p51 (int_imm_out)--25.3 prop 1/10/92 Additional tasks: - Pbus short spec - description of interface chips - system model w/16M dram 4 4Mx1 ?? make sure address is split appropriately to look like 16M chip. 1/13/92 Timing concerns on fsmchip: p45 (pc [1])--22.4 prop (ok) p46 (pc [0])--22.4 prop (ok) p48 (sv_ld)--27.5 prop (14.5 setup in ctlsvchip) p30 (sld)--26.5 prop p42 (ps16)--32.1 prop p41 (pspty)--30.3 prop p39 (pldec)--26.4 prop p37 (ldctl)--28.4 prop 1/13/92 Timing concerns on dataregs: p49 (sv_sel)--22.8 prop p5-p12 (pd [7:0])--22.9 prop 1/16/92 /sim/nhm/ctv1.exp produces invalid sync interrupts. note: this experiment did not initialize properly with dcam1--check it out. 1/20/92 Double the Sparcstation memory. 1/20/92 dcam1 size w/2K Sbus memory = 27615388 (after a 1000 ns delay) dcam1 size w/128K Sbus memory = 27615388 (after a 1000 ns delay) 1/20/92 We need to be able to multipurpose pins (4--chips 0 & 1) glue pins--chip 0 only (6) interface data bus parity and contention (1 bit--chip 0) force invalid sync (1) (01110, 0100, etc.) selection (bits 19-16): 0 - chip 0 glue 0 1 - chip 0 glue 1 2 - chip 0 glue 2 3 - chip 0 glue 3 4 - chip 0 glue 4 5 - chip 0 glue 5 6 - chip 0 mpa 7 - chip 0 mpb 8 - chip 1 mpa 9 - chip 1 mpb 10 - chip 0 interface data 11 - chip 0 sync bits 21-20: 0 - disable 1 - force to 1 2 - force to 0 3 - force pattern (single clock width pulse--done only when cam clock is running!) 1/23/92 Added bits to command register to enable/disable exceptions caused by cam interrupts and timeouts. 1/23/92 To change the value of the weight symbol in the vlsi tools, select "set attr" on the popup (doit) menu and click the right button on the icon. The weight symbol is found in the library "portable/Logic Assistant/ChipComp symbols". 1/23/92 Find a way to break the glue connections on chip 1 of the 4 chip module so the force vectors will work. This is not necessary per nhm 1/27/92. (see mail) 1/27/92 Modify ctlsv vectors to test enable and disable of cam interrupt and timeout exceptions. 2/3/92 Need to exercise rsin and right data on cam chip--use glue decodes to force this pin since the glue is tested another way now. 2/4/92 In Verilog, use the $freezewaves command to prevent constant screen updates during simulation. 2/10/92 Check the code that eliminates dead cycles. --Found that we need to wait for lsout to go low after accessing the scan-io register (reg 16) because the dram state machine needs time to run. 2/10/92 Set up to simulate slow pullups/pulldowns in Verilog. 2/11/92 VTI wants to use triple layer metal process to make the design fit. 2/12/92 Using x2.4.error.exp, the vector eater/clock killer produced 2766 vectors from 4024 clock cycles, a 31 percent saving with VECTOR_OFF_DELAY set to 8. Using x2.4.error.exp, the vector eater/clock killer produced 2507 vectors from 4135 clock cycles, a 39 percent saving with VECTOR_OFF_DELAY set to 4. Using x2.4.error.exp, the vector eater/clock killer produced 2337 vectors from 4153 clock cycles, a 43 percent saving with VECTOR_OFF_DELAY set to 2. x2.4.error.exp fails with VECTOR_OFF_DELAY set to 1. 2/13/92 Got the .pst (predictive capacitance file) from K.C. today. When this file is read into the timing verifier, it shows a capacitance of 23.17 pf on internal node sd_dr_n! However, the .rpa file shows this node to have "only" 15 pf. At first I thought I should set inccap and defcap to 0 before loading the .pst file, but this turned out not to make a difference. Still don't know the answer! 2/20/92 There is a problem with sys14 initializing; the cam status line goes to x. Use rcam sys14b and /sim/nhm/msr.exp to reproduce problem. 2/20/92 In the gate assistant's capacitance file chip_eval.pst, there is a node with the following name: U8.U2.U188.q_n[-1] Don't know how this happened. 2/20/92 Use set break and set nobreak in qtv to get desired paths in chip. 2/24/92 Drivers used in system simulation: bd4 pc6o11 pc6o12 pc6o41 pc6o42 pc6o45 pt6o11 pt6o41 2/24/92 Did some tests of Verilog's back annotation stuff using files: test_slow.v test_slow.vc test_slow.dat The simulation was invoked with the command: cam test_slow -s -i test_slow.dat Where cam invokes verilog and the command file test_slow.vc. The test_slow.dat file has the back annotation commands, which apparently must be entered in interactive mode. The last line of this file has a . (period) to start the simulation. The manual is a bit confusing as to whether the back annotation of an instance affects only that instance or ALL instances of the same module type. It appears that it only affects the specified instance. Note that the $update_timing command must be invoked for each scope specified. 2/24/92 Tom might want to do "evaluate floor plan" on the placement Norm did (on im3). 2/24/92 2:05 pm Called Cadence cust support (800-223-3622)--Sandy re pullup simulation. An app eng will call back; ref # 70.138. 2/24/92 approx 3:00 pm Al Kozlowski called back. 2/24/92 3:45 pm Sandy called back; she says they have solution to the pullup problem & will fax it this afternoon. 2/25/92 11:45 am Called Sandi at Cadence to find about getting dtran model. She will talk to Al Koslowski about it; he will call back. 2/25/92 To make a flattened netlist that qtv can "pipe", use the net utility: load [la]chip write (pipeflat) This will generate the flattened netlist file chip_f.nls. 2/26/92 To use named events in Verilog, first declare the event, then use the @ function to trigger on the event. The actual event occurs when the statement -> event_name; is executed. Example: integer a, b; event namex; @(namex) a = b; initial if (b == 1) -> namex; 2/26/92 Eric at Cadence-- still ref # 70.138 - Do we really need version 1.6 to link dtran stuff? - Can we get updated version of Verilog if necessary? - Can we get the necessary source files? He will have an app eng call back. 2/26/92 Another Verilog question--is the $count_drivers system function gone, or does it just have a new name? 2/26/92 Dave Zopf called--he will email the dtran stuff. He says the $count_drivers function should work; he will find an example and email it later. Someone named Karen is working on getting us the latest version of Verilog. Dave's personal number is 508-934-0431. 3/2/92 Found out that the name of the above function is $countdrivers, not $count_drivers. This works much better! 3/9/92 Timing concerns: ctlsvchip: p13 - p27 = 23.1 (fall) p13 - p28 = 23.1 (fall) p13 - p29 = 23.1 (fall) p13 - p33 = 23.1 (fall) p13 - p34 = 23.1 (fall) 3/9/92 VLSI-- Tom Donelly Mike Rockenhauser decwrl!vlsisj!bos1!rocky vlsisj!bos1!rocky@decwrl.dec.com could use this address: decwrl!vlsisj!bos1!rocky@uunet.uu.net send netlist and pst netlist /netlist.lib command mentioned in /cam/vlsi/patches/README was for previous release and should be removed from current .boo file (per Tom Donelly). compress /* (makes .Z) */ /* the second parameter is what the decoded filename will be */ uuencode .Z .Z >! use the ~r command in mail to send the file. 3/9/92 Use "comp" command to send mail; this gives you an emacs window to "compose" with. Use meta-x insert-file to add text from another file. When done, do C-x C-w to write, C-x C-c to exit, and answer "What now?" with "send" to send the mail. 3/10/92 2:10 pm VLSI--Mike Rockenhauser He got the netlist and pst files; he gets a bunch of netlist error when he tries to load the .pst file. Could it be that the netlist and pst files don't agree? 3/11/92 When using the cat < ( sh -c 'echo xxx >&2; echo yyy' ) >! jjj xxx im4:/im/faust/junk1 > cat jjj yyy # multiple string substitution by piping through sed im4:/im/faust/junk1 > echo a b c d | sed -e "s/a/x/g" -e "s/b/y/g" x y c d im4:/im/faust/junk1 > 3/25/92 The SCAN signal is daisy chained within the box; it goes in and out of modules via multipurpose pins. Add an option to the cam script to hook up the scan signal on the 212 model. 3/26/92 Timing concerns: ctlsvchip: p27 = 22.6 fall (fixed w/8ma buffer) p28 = 22.8 fall (fixed w/8ma buffer) p23 = 27.2 rise (psd_rc) (eliminated buffer on ldctl; changed (to 4-1 mux in csvsel) p24 = 23.5 rise (sync_out) (moved mux in front of ff in sync_encode) p46 = 26.5 rise (od_ri) (op_data ok; need to rerun with break in cam clock to check interface reset) p51 = 25.2 fall (int_imm_out) (changed to 4-1 mux in csvsel--retest) fsmchip: p43 = 22.8 rise (ps8) (added buffer) p50 = 25.2 rise (sclr_n) p48 = 25.0 rise (sv_ld) (added buffer) p42 = 31.5 fall (ps16) (added buffer) p41 = 29.8 fall (pspty) (added buffer) p40 = 23.6 rise (pcwr) (added buffer) p39 = 27.7 fall (pldec) p37 = 27.5 fall (ldctl) (added buffer) 3/26/92 Added 8ma slew driver to pin P24 (iosel and sync_out) Added 8ma slew driver to pins p27 through p42. Added 8ma normal drivers to p5, p6, p28, and p29. NOTE!! Don't forget to update pinout-phys!! (done 3/30/92) 3/30/92 Holdups on bus during opcode transmission cause a problem, elicited by running cam 1 with fload /im/cam8/vsim/verify/exp/ecsr.1.12.exp 3/31/92 pctlfsm.sm is in the middle of changes; work on generation of op_en in load_op state. 4/1/92 The problem with cam 112 is that with only one chip per module, we get rsout and ioout from "inside" the previous cam chip, so the scheme of initializing boxes one by one doesn't work. Since we are about to change the way these signals are output from the cam chip, we had better make sure that they wake up disabled. 4/1/92 Finish changes related to "holdups during opcode" problem. 4/1/92 Module selection register codes: selection code bits to be matched MSR internal target 000 MIDR 0 010 MIDR 1 100 MIDR LIR 110 Glue-AND 0 001 GIDR 0 011 GIDR 1 101 GIDR LIR 111 don't care 4/2/92 7:40 am Start up cam 22 +cdebug b with /sim/nhm/sequential.err2.exp for Tom. 4/2/92 Change pullup delay in slow_pull to 10000 nsec and find out why it doesn't work with the one chip model. 4/6/92 Change pbus resistors to pulldowns instead of pullups. Also, need longer delays on slow pullups/pulldowns. 4/8/92 Fix the timing violation problem in the sync generator. 4/15/92 On Tom's sequential.err2.exp with cam 212 b, what appears to be happening is that layer 1 of module 0 (closest to the interface) first gets its multipurpose register A programmed to be scan input; then, after module 1 is programmed, layer 1 of module 0 is reprogrammed so that its multipurpose A is status in (because module 0 should ignore the scan input pin). Since the output select of pin p53 is the lsb of the MPA reg, this pin switches from rsout to lsout--not the desired result! 4/15/92 On the problem with /sim/verify/kick.1d.xy.exp with model cam 13 b, the problem is that the cam chip does bus holdups after reading scan-io; we need to do the programmed wait after scan-io reads as well as writes (we thought we could get away without this because the bus has to turn around, but the holdups propagate backwards anyhow). 4/16/92 cam fullctlsvb takes 54 meg of memory. cam fulldataa takes 55 meg of memory. 4/16/92 Meeting at VLSI Thursday 4/23/92 10:00 am directions to vlsi: Take i-95 N to route 125 exit. Go right, then take 1st left onto Ballardvale Street. Go past Charles River Breeding Labs. Take next right onto driveway (before the road goes right). Go to higher of two buildings. There are two entrances--take the wrong one first. 4/17/92 Check whether we should remove *internal* pulldown on p52 (this is sbus signal sb_rd). 4/22/92 Finish fixing break files for u1, u8, u9, u10 and do another chip_tv run. 4/27/92 Try modifying node logic to turn off rsout when there is a holdup in the cam chip (use c_lsout). Done 4/27/92 in /im/cam8/vsim/df. 4/27/92 If the vlsi software locks up so you can't check anything out, delete the vlsi.lck file in the controlled directory. 4/27/92 Remember that the pullups in qsim have the source and drain swapped. (a pullup is specified as: transistor p vss pinname vdd 4/28/92 newx sets the multi register to 002 in layer 0 and 041 in layer 1. 4/30/92 Interface reset hangs when "fullfsm" and "fullcam" models are run. 4/30/92 Timing on fsmchip from ack -> sdr and ptr_inc (30 pf on outputs assumed): rise fall p4 -> p11 (ack[0] -> sdr) = 9.4 8.7 p2 -> p9 (ack[2] -> ptr_inc) = 9.5 9.9 p3 -> p9 (ack[1] -> ptr_inc) = 9.8 8.9 p4 -> p9 (ack[0] -> ptr_inc) = 9.7 8.9 5/5/92 Use XtoPS (X to PostScript) to write a picture of a window to a file XtoPS 5/5/92 Timing problems: - sb_rd to sv_en to u10.u1.u125.u174.u1$1.k (on int_reg) fixed by lowering cap on sv_en to 30 pf - clk -> donep (U1) -> pcwr speeded up one detect in ctlsvchip, reduced cap to 30 pf 5/6/92 Norm will create a "newxa" or something similar which expects pullups instead of pulldowns on the pbus. 5/7/92 Slow timing path: - donep (must propagate from clk to output of u2, thru u1, and set up in u3. The total cycle time is 42.5 using today's version of chip.pst. 5/11/92 The chip was sent to KC yesterday (via Email) at 2:30 pm. He says that he received it at 11:00 pm and didn't start layout until today. He requested that we send him a flattened netlist so he can do the route on a faster machine. 5/11/92 2:50 pm Sent flattened netlist to KC as requested. 5/11/92 Full speed simulation worked with 40 ns cycle and 16 nsec setup. Full speed simulation failed with 40 ns cycle and 15 nsec setup. 5/12/92 1:35 pm KC has new layout--no unroutes. He will Email it to us immediately. 5/13/92 KC's email address: vlsisj!merlot!karlb@decwrl.dec.com 5/13/92 chip.pst.pass2 setup = 15 ns sys1_cap: sv_ld = 30 pf sv_on = 20 pf sdr = 0 pf FAILS! chip.pst.pass2 setup = 15 ns sys1_cap: sv_ld = 30 pf sv_on = 10 pf sdr = 0 pf OK! chip.pst.pass2 setup = 15 ns sys1_cap: sv_ld = 30 pf sv_on = 10 pf sdr = 40 pf OK! chip.pst.pass2 setup = 15 ns sys1_cap: sv_ld = 40 pf sv_on = 10 pf sdr = 40 pf OK! 5/14/92 The worst timing problem in the interface seems to be the sv_on signal coming from the dataregs to the fsmchip. The bad path is from the sb_ack, sb_as_n, and sb_sel_n inputs to the sv_on output. When we gave KC a flattened netlist to use for routing, this path got slower. The reason is mainly because the mux that drives the output buffer had a high capacitance on its output because the weight that was on it got lost. This "lost weight" problem occurs because of the use of the flattened netlist. To fix the bad path, I would like weights on the following nodes: u8.u13.u10.zn u8.u13.u11.zn u8.u13.u3.zn u8.u13.u1.qn u8.u13.u4.z u8.u13.u9.z u541.z 5/14/92 In order to make at-speed interface tests produce the same output for qsim and Verilog, the Verilog simulation must be run with pullups instead of pulldowns on the pbus data lines, and the parameter "pullup_delay" in pull_slow.v should be set to 10 nsec. 5/18/92 To make chip.pst (dated 05/17/92 4:?? ) work at speed: - change bidirect buffer u1057 to pt6o42 (was pt6o41) (pin P1). - make sure that capacitance of signal ptr_inc on interface board is 30 pf or less. 5/18/92 Dave Power's Email address: vlsisj!tornado!dave@decwrl.dec.com 5/20/92 Ask KC if they can measure a critical path delay at test time. 5/20/92 testing w/nle file: x2.4.error: - works at 44 nsec cycle, 17 nsec setup - fails at 42 nsec cycle, 16 nsec setup - fails at 42 nsec cycle, 17 nsec setup scan-io.random: - works at delay factor .95 (40 nsec cycle, 15 nsec setup) - works at delay factor .97 (40 nsec cycle, 15 nsec setup) - works at delay factor .98 (40 nsec cycle, 15 nsec setup) - works at delay factor .99 (40 nsec cycle, 15 nsec setup) - works at delay factor 1.00 (40 nsec cycle, 15 nsec setup) !!! 5/21/92 slow outputs: p27 (u10) (23.1) - driven by u10.u1.u124.u204$1.z p4 (u9) (22.6) - driven by u9.u78.u83.z p7 (u8) (23.5) - driven by u8.u1.u215.z p8 (u8) (???) - driven by p9 (u8) (22.7) - driven by u8.u1.u215.z p11 (u8) (???) - driven by 5/22/92 ivec simulation with chip.pst (5/22/92 14:16) - failed with delayfactor 1.00 - failed with delayfactor .98 5/26/92 slow outputs: p27 (u10) (23.2) (sbus data) p24 (u10) (22.6) (sync_out) p51 (u10) (???) (int_imm_dr_n)--check again p7 (u8) (25.4) (pdata_dr_n_d) 5/26/92 update ctlsvchip.edf.v, fsmchip.edf.v, chip.edf.v 5/26/92 Give KC a critical path to be measured at test time. We give him 2 pins, each to be measured during a SPECIFIC CYCLE during the SAME BLOCK OF VECTORS. 7/22/92 installing device driver in im11: change directory to /im/cam8/devdri type: touch cam.c make install 7/22/92 Worked on the hang problem when CAM module not plugged in. The problem is the interface is requesting infinite bursts from the SPARCstation. The problem disappeared and would not come back after a few minutes. The test was done on im3. Norm says the first interface fails consistently. Will try later. The second interface board (the one with the handshake fix) causes timeouts when test16.exp is run. The problem occurs whenever a register read is attempted. All signals to CAM look good both with scope and logic analyzer (timing looks fine). Guessing that the problem might be related to running CAM at 25 MHz, I tried the first ("good") interface on im11, which has a 25 MHz clock. It fails test16.exp with a CAM interrupt rather than a timeout interrupt, but fails after a few (3-5) tries at reading the multi register. select 1 reg! multi *step* multi read *step* 7/22/92 Was able to reproduce the "Sparcstation hang when CAM not plugged in" problem. There is a problem in the sbus control which allows the sctlfsm to clear the error status before an hstop can be sent back from the ctlsvchip. This should be fixable using the existing pal. Verilog pseudo-code for fix: dfctnb ux1 (ux1q, ux1qn, fsmchip-39(tmint), sb_clk); or02d1 ux2 (fsmchip-10(hstop'), hstop(from ctlsvchip0), ux1q); 7/23/92 Couldn't duplicate the above problem in simulation on the first try-- hstop is already asserted when the timeout occurs. Will have to check it out further after vacation. 9/16/92 Infinite loop in Forth is begin...again 10/22/92 Working on 24 MHz bug (bug24.exp). Had trouble reproducing problem at first; then made a loop to execute the experiment continuously--this made the problem happen immediately. The logic analyzer kept failing its front panel test, then finally started working. I put probes on the following signals: pb_clk (pin 1 of lspatch) iosel (lspatch-5) pb_data[0] (u4-44) eofout/lsin (lspatch-18) eofin/lsout (lspatch-2) pb_eosi (u1-4) Now the test runs continuously without failing! 11/5/92 Working on the diags25.exp problem. The system fails to iniialize with the logic analyzer probes on; the one probe found be responsible is the one on IOSEL. Initialization could be done by switching the clock jumper over to the sbus clock (this was on im1--20 MHz). The problem now is that a cam interrupt and a timeout interrupt occur when a scan-io read is attempted. The opcode transmission looks OK and I can't view the previous transfer, so I'm not sure what the problem is. 11/12/92 Working on diags.exp problem. With NO lspatch and 25 MHz (async) clock, a timeout occurs when a read of register 23 is attempted. This is probably the first attempted read since triggering on eofin=1 produces no trigger during the test. There is no problem when we use the 20 MHz Sbus clock (sync). With the lspatch fix in and using the 25 MHz clock (async), the problem is the same as above; failure to read register 23. Experimenting with trigger count of iosels--problem takes n counts to occur where: 925 < n < 935 this count is inconsistent; sometimes it takes [much?] less time to fail. 11/19/92 Worked on diags.exp problem. Connected logic analyzer to cam module (layer 13). Now diags.exp will not initialize even synchronously unless I disconnect the probe on iosel. Looked at iosel on scope and found 3 volts of undershoot! We need to fix this.