Interface chip pin changes

	Was		Is		Chip(s)

	error		sbus_err	ctlsvchip, fsmchip
	psh		op_shft		ctlsvchip, fsmchip
	sfi    		sync_dec_in	ctlsvchip
	tmcmint		suspend		ctlsvchip, fsmchip
	---    		partial_xfer	ctlsvchip, fsmchip
	---    		clr_suspend	ctlsvchip, fsmchip
	---    		sync_out	ctlsvchip
	sfi_imm		int_imm_out	ctlsvchip
	int_dr_n	---		ctlsvchip
	---		int_imm_dr_n	ctlsvchip (not external)
	decout		sync_dec_out	ctlsvchip (same pin as
							sync_dec)
	---		sync_dec_dr_n	ctlsvchip (not external)
	---		sb_reset_n      fsmchip
	---		ifc_rst_n       fsmchip
	sclr_n		sclr_n          fsmchip--changed from input to output
	sb_reset_n	---		ctlsvchip
	od		op_data		dataregs
	cam_rst_in_n	---		ctlsvchip
	svld		sv_ld		ctlsvchip, fsmchip
	svdr		sv_en		ctlsvchip, fsmchip
	sva [1]		sb_pa [3]	ctlsvchip
	sva [0]		sb_pa [2]	ctlsvchip
	hsig		hnp_sel		ctlsvchip
	sdr_s		sb_va_en	ctlsvchip, fsmchip
	hw_cw		hw_rd		ctlsvchip
	rd_flg8		cw_flg8		ctlsvchip

5/16/91

		signal		is	was

  ctlsvchip:
		hnp_sel		p47	p23
		psd_rc		p23	p47

  fsmchip:
		sv_ld		p48	p23
		eofout		p23	p48

		sv_en		p36	p24
		iosel		p24	p36

  dataregs:
		op_data		p43	p5
		flg8		p44	p6
		pcwr_d		p45	p7
		pc_d[1]		p46	p8
		pc_d[0]		p47	p9
		eofin		p48	p10
		immed		p49	p11
		eofout		p50	p12

		pb_d[7]		p5	p43
		pb_d[6]		p6	p44
		pb_d[5]		p7	p45
		pb_d[4]		p8	p46
		pb_d[3]		p9	p47
		pb_d[2]		p10	p48
		pb_d[1]		p11	p49
		pb_d[0]		p12	p50

9/3/91

	These changes are to bring eofin into both ctlsvchips and
	to bring rd and immed from the low ctlsvchip to the high
	ctlsvchip to fix timing problem involving the pbus word
	counter.

	Was			Is			Chip(s)

	sync_dec_in (p48)	imm_sync_in (p53)	ctlsvchip
	zin (p3)		rdin_zin (p3)		ctlsvchip
	--- (p53)		eofin (p48)		ctlsvchip