pin counts for interface chips

vss = 5
vdd = 4
vss1 = 2
vdd1 = 2

ctlsvchip = 53
fsmchip = 52 (spare:  p9)
dataregs = 52 (spare:  p53)

ctlsvchip:
        inout [15:0]
                sb_d;
				16
        output
                hw_rd,
                cw_flg8,
                hstop,
                od_ri,
                donep,
                incout,
                hnp_sel,
                psd_rc,
                int_imm,
                imm_sync_in,
		sync_out,
		clr_suspend;
				12
        input [2:0]
                sc;
                                 3
        input [3:2]
                sb_pa;
                                 2
        input
                sclr_n,
		partial_xfer,
                eosi,
		sb_bg_n,
                incadr,
                sbus_err,
                tmint,
                op_shift,
                pb_clk,
                tst,
                ldctl,
                sv_en,
		eofin,
                sv_ld,
                sld,
                suspend,
                sel,
                zin,
                sb_clk,
                decin;
				20

fsmchip:
        inout [2:0]
                sb_ack_;
				3
        inout
                sb_rd;
				1
        output [1:0]
                pc;
				2
        output [2:0]
                sc;
				3
        output
                param_dr_n, (test only)
                incadr,
                sld,
                pdav, (test only)
                sbus_err,
                dr,
                ps8,
                ps16,
                pspty,
                pcwr, (test only)
                pldec,
                ldctl,
                sv_en,
                op_shift,
                tmint,
                sv_ld,
                sdr,
		sclr_n,
                eofout,
		partial_xfr,
                prom_dr_n,
                iosel,
                sb_br;

				23
        input
                ifc_rst_n,
                eosi,
                sb_bg,
                hstop,
		clr_suspend,
                sb_lerr,
                sv_on,
                pb_clk,
                sv_sel,
                rd,
                eofin,
                donep,
                psd,
                cw,
                suspend,
                flg8,
                sb_reset_n,
                sb_clk,
                sb_pa,
                immed;

				20

dataregs:
        inout [7:0]
                pb_d,
                sb_dh,
                sb_dl;
				24
        inout [2:0]
                sb_sz;
				 3
        output
                sv_on,
                sv_sel,
                pdata_dr_n, (not external)
                sdata_dr_n; (not external)
				 2
        input [2:0]
                sc;
				 3
        input [1:0]
                pc;
				 2
        input
                sclr_n,
                sld,
                flg8,
                op_data,
                op_shift,
                pb_clk,
                sb_clk,
                eofin,
                eofout,
                pspty,
                sb_sel,
                immed,
                dr,
                ps16,
		sb_bg_n,
                sb_as,
                sdr,
                ps8;

				 18