To all Verilog CAM model users,

     The problems with the July 25 release were due to a
bug in sys12.v, sys13.v, and sys14.v which shorted together
the right interface bus data pins for all the cam chips.
This did not cause a problem in the July 7 release because
that version of the cam chip defaulted to the cam hardware
being on the left side of the node logic.

                             Doug