PHYS_PIN PIN I/O CAM DATAREGS FSMCHIP CTLSVCHIP PAD TYPE SELECT (S1,S0) 00 01 10 11 01 P25 I CLK sclr_n_d ifc_rst_n_f sclr_n_c TTL input 01 O 01 EN 02 P62 I VSS VSS VSS VSS 03 P5 I MPB_IN pd_in_d[7] partial_xfer_c CMOS 4ma PU 03 O MPB_OUT pd_out_d[7] param_dr_n_f 03 EN MPB_EN_N pdata_dr_n_d VSS VDD U1003.z 04 P6 I MPA_IN pd_in_d[6] eosi_f eosi_c CMOS 4ma PU 04 O MPA_OUT pd_out_d[6] 04 EN MPA_EN_N pdata_dr_n_d VDD VDD U1007.z 05 P4 I DISP_IN sb_sz_d[0] ack_in_f[0] decin_c TTL 2ma NP 05 O DISP_OUT VSS ack_out_f[0] 05 EN DISP_EN_N param_dr_n_d ack_dr_n_f VDD U855.z 06 P34 I sdh_in_d[0] sbdin_c[8] TTL 2ma PU 06 O DA[10] sdh_out_d[0] incadr_f sbdout_c[8] 06 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U691.z 07 P30 I sdh_in_d[4] sbdin_c[12] TTL 2ma PU 07 O DOE_N sdh_out_d[4] sld_f sbdout_c[12] 07 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U667.z 08 P31 I sdh_in_d[3] sbdin_c[11] TTL 2ma PU 08 O DCAS_N sdh_out_d[3] sc_f[2] sbdout_c[11] 08 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U695.z 09 P16 I DDIN[2] sc_d[2] sb_bg_f incadr_c TTL 2ma PU 09 O DDOUT[2] 09 EN DOE_N VDD VDD VDD U655.z 10 P15 I DDIN[3] sld_d hstop_f sbus_err_c TTL 2ma PU 10 O DDOUT[3] 10 EN DOE_N VDD VDD VDD U654.z 11 P17 I DDIN[1] sc_d[1] clr_suspend_f sc_c[2] TTL 2ma PU 11 O DDOUT[1] 11 EN DOE_N VDD VDD VDD U656.z 12 P56 I VDD VDD VDD VDD 13 P63 I VSS VSS VSS VSS 14 P18 I DDIN[0] sc_d[0] sc_c[1] TTL 2ma PU 14 O DDOUT[0] pdav_f 14 EN DOE_N VDD VSS VDD U657.z 15 P32 I sdh_in_d[2] sbdin_c[10] TTL 2ma PU 15 O DWE_N sdh_out_d[2] sc_f[1] sbdout_c[10] 15 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U693.z 16 P33 I sdh_in_d[1] sbdin_c[9] TTL 2ma PU 16 O DRAS_N sdh_out_d[1] sc_f[0] sbdout_c[9] 16 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U692.z 17 P35 I sdl_in_d[7] sbdin_c[7] TTL 2ma PU 17 O DA[9] sdl_out_d[7] sbus_err_f sbdout_c[7] 17 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U690.z 18 P64 I VSS VSS VSS VSS 19 P44 I flg8_d rd_in_c TTL 2ma PU 19 O DA[0] dr_f hw_rd_c 19 EN VSS VDD VSS rd_dr_n_c U951.z 20 P43 I op_data_d TTL 2ma PU 20 O DA[1] ps8_f cw_flg8_c 20 EN VSS VDD VSS VSS U94.z 21 P42 I sdl_in_d[0] sbdin_c[0] TTL 2ma PU 21 O DA[2] sdl_out_d[0] ps16_f sbdout_c[0] 21 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U681.z 22 P41 I sdl_in_d[1] sbdin_c[1] TTL 2ma PU 22 O DA[3] sdl_out_d[1] pspty_f sbdout_c[1] 22 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U682.z 23 P65 I VSS VSS VSS VSS 24 P57 I VDD VDD VDD VDD 25 P40 I sdl_in_d[2] sbdin_c[2] TTL 2ma PU 25 O DA[4] sdl_out_d[2] pcwr_f sbdout_c[2] 25 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U683.z 26 P39 I sdl_in_d[3] sbdin_c[3] TTL 2ma PU 26 O DA[5] sdl_out_d[3] pldec_f sbdout_c[3] 26 EN VSS sdata_dr_n_d VSS sbd_dr_n_c 27 P38 I sdl_in_d[4] sb_lerr_f sbdin_c[4] TTL 2ma PU 27 O DA[6] sdl_out_d[4] sbdout_c[4] 27 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U1103.z 28 P37 I sdl_in_d[5] sbdin_c[5] TTL 2ma PU 28 O DA[7] sdl_out_d[5] ldctl_f sbdout_c[5] 28 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U687.z 29 P36 I sdl_in_d[6] sbdin_c[6] TTL 2ma PU 29 O DA[8] sdl_out_d[6] sv_en_f sbdout_c[6] 29 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U689.z 30 P45 I GLUE_IN[5] CMOS 2ma PU 30 O pc_f[1] hstop_c 30 EN VDD VDD VSS VSS U1029.zn 31 P7 I GLUE_CMP[5] pd_in_d[5] sv_on_f tmint_c CMOS 4ma PU 31 O GLUE_OUT[5] pd_out_d[5] 31 EN GLUE_EN_N[5] pdata_dr_n_d VDD VDD U1012.z 32 P46 I GLUE_IN[4] pc_d[1] CMOS 2ma PU 32 O pc_f[0] od_ri_c 32 EN VDD VDD VSS VSS U1031.zn 33 P8 I GLUE_CMP[4] pd_in_d[4] op_shift_c CMOS 4ma PU 33 O GLUE_OUT[4] pd_out_d[4] op_shift_f 33 EN GLUE_EN_N[4] pdata_dr_n_d VDD VDD U1015.z 34 P66 I VSS VSS VSS VSS 35 P26 I CLR_N pb_clk_d pb_clk_f pb_clk_c TTL input 35 O 35 EN none none none none 36 P58 I VDD VDD VDD VDD 37 P2 I SAD_IN sb_sz_d[2] ack_in_f[2] tst_c TTL 2ma PU 37 O SAD_OUT VDD ack_out_f[2] 37 EN SAD_EN_N param_dr_n_d ack_dr_n_f VDD U543.z 38 P9 I GLUE_CMP[3] pd_in_d[3] ldctl_c CMOS 4ma PU 38 O GLUE_OUT[3] pd_out_d[3] sb_va_en_f 38 EN GLUE_EN_N[3] pdata_dr_n_d VSS VDD U1017.z 39 P47 I GLUE_IN[3] pc_d[0] sb_pa_c[3] CMOS 2ma PU 39 O tmint_f 39 EN VDD VDD VSS VDD U1089.zn 40 P10 I GLUE_CMP[2] pd_in_d[2] sv_sel_f sv_en_c CMOS 4ma PU 40 O GLUE_OUT[2] pd_out_d[2] 40 EN GLUE_EN_N[2] pdata_dr_n_d VDD VDD U1019.z 41 P48 I GLUE_IN[2] eofin_d eofin_c CMOS 2ma PU 41 O sv_ld_f 41 EN VDD VDD VSS VDD U929.z 42 P11 I GLUE_CMP[1] pd_in_d[1] CMOS 4ma PU 42 O GLUE_OUT[1] pd_out_d[1] sdr_f donep_c 42 EN GLUE_EN_N[1] pdata_dr_n_d VSS VSS U1021.z 43 P49 I GLUE_IN[1] rd_f CMOS 2ma PU 43 O sv_sel_d incout_c 43 EN VDD VSS VDD VSS U1091.zn 44 P12 I GLUE_CMP[0] pd_in_d[0] eofin_f hnp_sel_in_c CMOS 4ma PU 44 O GLUE_OUT[0] pd_out_d[0] hnp_sel_out_c 44 EN GLUE_EN_N[0] pdata_dr_n_d VDD hnp_sel_dr_n_c U1023.z 45 P50 I GLUE_IN[0] eofout_d sv_ld_c CMOS 2ma PU 45 O sclr_n_f 45 EN VDD VDD VSS VSS U1105.zn 46 P67 I VSS VSS VSS VSS 47 P59 I VDD VDD VDD VDD 48 P23 I N_DL_IN pspty_d CMOS 16ma NP 48 O N_DOUT eofout_f psd_rc_c 48 EN N_DLEN_N VDD VSS VSS U661.z 49 P51 I sb_sel_d int_imm_in_c TTL 2ma PU 49 O DA[11] partial_xfer_f int_imm_out_c 49 EN VSS VDD VSS int_imm_dr_n_c U1106.z 50 P54 I S0 S0 S0 S0 TTL input PU 50 O 50 EN VDD VDD VDD VDD 51 P55 I S1 S1 S1 S1 TTL input PU 51 O 51 EN VDD VDD VDD VDD 52 P20 I N_IOSEL_N immed_d donep_f sld_c CMOS input NP 52 O 52 EN none none none none 53 P60 I VDD VDD VDD VDD 54 P68 I VSS VSS VSS VSS 55 P19 I N_RSIN dr_d psd_f sc_c[0] CMOS input NP 55 O 55 EN none none none none 56 P22 I N_LSIN ps16_d suspend_c CMOS 2ma NP 56 O prom_dr_n_f 56 EN VDD VDD VSS VDD U1097.zn 57 P29 I sdh_in_d[5] cw_f sbdin_c[13] TTL 2ma PU 57 O SAA sdh_out_d[5] sbdout_c[13] 57 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U1101.z 58 P1 I INT_IN_N sel_c TTL 2ma NP 58 O VSS sv_on_d suspend_f Schmitt trigger input 58 EN INT_EN_N VSS VSS VDD U540.z 59 P28 I sdh_in_d[6] flg8_f sbdin_c[14] TTL 2ma PU 59 O SBA sdh_out_d[6] sbdout_c[14] 59 EN VSS sdata_dr_n_d VDD sbd_dr_n_c U1100.z 60 P3 I SBD_IN sb_sz_d[1] ack_in_f[1] zin_c TTL 2ma PU 60 O SBD_OUT VSS ack_out_f[1] 60 EN SBD_EN_N param_dr_n_d ack_dr_n_f VDD U557.z 61 P53 I sb_reset_n_f imm_sync_in_c TTL 2ma PU 61 O TEST2_OUT 61 EN VSS VSS VDD VSS U970.z 62 P13 I FLY_IN sb_clk_d sb_clk_f sb_clk_c TTL input 62 O 62 EN none none none none 63 P24 I N_DR_IN param_dr_n_d CMOS 4ma NP 63 O N_DOUT iosel_f sync_out_c 63 EN N_DREN_N VDD VSS VSS U500.z 64 P52 I sb_as_d sb_rd_in_f TTL 2ma PU 64 O TEST1_OUT sb_rd_out_f clr_suspend_c 64 EN VSS VDD param_dr_n_f VSS U1095.z 65 P14 I MODSEL_IN sdr_d sb_pa_f sb_pa_c[2] TTL 4ma NP 65 O MODSEL_OUT 65 EN MODSEL_EN VDD VDD VDD 66 P21 I SYNC ps8_d immed_f sb_va_en_c CMOS input NP 66 O 66 EN none none none none 67 P27 I sdh_in_d[7] sbdin_c[15] TTL 2ma PU 67 O FLY_OUT sdh_out_d[7] sb_br_f sbdout_c[15] 67 EN VSS sdata_dr_n_d VSS sbd_dr_n_c U664.z 68 P61 I VDD VDD VDD VDD