Test Plan for Interface and Node Logic

General

  - Synchronizers--test with fast and slow pb_clk

  - Test PROM

ctlsvchip

  - eosi decoding (interrupt and scan status)

  - dncntr16 (PBus xfer count)

  - opcode register

  - next address pointer

  - control regs
    - 8 bit mode
    - immediate mode
      - lengths of 0-6
      - read (noop)
    - host wait
    - host jump
    - cam wait (for end of scan)

  - slave regs
    - cam reset
    - interface reset
    - timeout
    - interrupts
      - soft interrupt
      - pbus timeout
      - sbus error
      - cam interrupt

fsmchip

  - SBus bug fix

  - end of scan decode (sctlfsm)

  - sparfsm

  - sctlfsm

  - scamwrfsm

  - scamrdfsm

  - pctlfsm

  - pwrfsm

  - prdfsm

  - SBus error decode

dataregs

  - slave decoding

  - data out regs
    - normal mode
    - 8 bit mode

  - data in regs
    - data available flags
    - parity generation
    - immediate mode
    - block mode

Node logic

  - variables:

    - read/write
    - iosel high time (1-6)
    - eofout--16 possible values at each edge of iosel
    - rs1in--16 possible values at each edge of iosel
    - ldata--16 possible values at each edge of iosel
    - rdata--16 possible values at each edge of iosel