Verilog SBus model

Yatin,

      I am working for Norm Margolus and Tom Toffoli at the
MIT Lab for Computer Science, and I'm having trouble using
the memory model included with the Verilog SBus model.  I
have an SBus master which I want to access the memory in
bursts of four words.  I am using the dma_master task to
grant the bus to my master, but I am unable to get any
response from the memory.  If you could tell me what I need
to do I would appreciate it.
     I can be reached Tuesdays at 617-253-2612 and other days
at 508-533-8886, or faust@im.lcs.mit.edu

     Thanks.

Doug Faust