Procedure to verify a Verilog model against a VLSI design Rev C 5/2/91 1. Use Verilog to write the inputs to a (.tbl) file in tabular format, with a semicolon at the end of each line, omitting the clock. The first line of the file should be: PINORDER input1, input2, ... inputN; where the input names are in the same order as the signals below them appear. This line may be split up into more than one line by placing the continuation character, a hyphen (must be preceded by a space), at the end of each line to be continued. Sample .tbl file: ------------------------------------------------------------------------ | | PINORDER shft_cnt_n, clr, d, cin; x x x x; 0 1 0 0; 0 0 0 0; 0 0 1 0; 0 0 0 1; 0 0 0 1; | | ------------------------------------------------------------------------ 2. The verilog file should also produce a file displaying the output signals in tabular format, with time displayed on the left in "short" ($stime) format. All vectors should be in hex format; exceptions to this will require additional radix declarations in the qsim command file (see the qs.vc example file below) (also see the SET RADIX command on page 6-74 of the mixed-mode simulator manual). The last line of the file must be all x's so qsim knows where to stop. An example output file: ------------------------------------------------------------------------ | | 250.0 x x 1250.0 x 0 2250.0 0 0 3250.0 0 0 4250.0 0 0 5250.0 1 0 6250.0 1 1 7250.0 2 0 8250.0 2 0 9250.0 3 0 10250.0 3 3 11250.0 x x | | ------------------------------------------------------------------------ 3. A .wvs (VLSI wave simulation) file must be created which reads the .tbl file and generates a .sim file for use in VLSIqsim. The file which was used for testing is shown: ------------------------------------------------------------------------ | | # cntr_sr4.wvs # VLSI wave command file to test functional verification of # gate level designs with Verilog behavioral models GLOBAL CONSTANT clockrise = 250 ns, # clock (RTZ) timing clockfall = 750 ns, cycletime = 1000 ns, # test cycle period dataedge = 0 ns, # input (NRZ) timeset datastrobe = 900 ns ; # output sample time # specify test cycle period DURATION cycletime ; # define inputs and outputs RTZ "clk" EDGE clockrise clockfall ; INPUT "shft_cnt_n" EDGE dataedge ; INPUT "clr" EDGE dataedge ; INPUT "d" EDGE dataedge ; INPUT "cin" EDGE dataedge ; OUTPUT "q" STROBE datastrobe ; OUTPUT "cout" STROBE datastrobe ; GLOBALEND ; MAIN VARIABLE i ; "clk" <- RTZon ; i := 1 ; WHILE ( (i < 3) OR ( (i > 2) AND ("shft_cnt_n" NEQ x) ) ) DO BEGIN SETTABLE ("cntr_sr4", i) ; "shft_cnt_n" <- GETTABLE ("cntr_sr4", "shft_cnt_n") CYCLE i ; SETTABLE ("cntr_sr4", i) ; "clr" <- GETTABLE ("cntr_sr4", "clr") CYCLE i ; SETTABLE ("cntr_sr4", i) ; "d" <- GETTABLE ("cntr_sr4", "d") CYCLE i ; SETTABLE ("cntr_sr4", i) ; "cin" <- GETTABLE ("cntr_sr4", "cin") CYCLE i ; END ; MAINEND ; | | ------------------------------------------------------------------------ 4. Now that the .wvs file is created, generate a .sim file using VLSIwave. I use the following C shell script to do this: ------------------------------------------------------------------------ | | rm wave.log vlsishell wave.log grep -c error wave.log | | ------------------------------------------------------------------------ The file wave.vc contains vlsishell commands as follows: ------------------------------------------------------------------------ | | utility wave load [wvs]cntr_sr4 go option tabular on format vlsiqsim write q q | | ------------------------------------------------------------------------ 5. Once the .sim file is created, make the following changes: a. change trace (dynamic, tabular) to trace (static, tabular) b. in the WATCH command: 1. delete (reportOnChange) 2. delete input signals, if any 6. Now generate the trace file by running VLSIqsim. I use the following C shell script to do this: ------------------------------------------------------------------------ | | rm qs.log vlsishell qs.log grep -c error qs.log | | ------------------------------------------------------------------------ The file qs.vc contains vlsishell commands as follows: ------------------------------------------------------------------------ | | qs load [la]cntr_sr4 node dummy set radix 16 set clock (report) dummy 0(250) ; 1(1000) 0 set options -tab set trace interval 1 load [sim]cntr_sr4 q q | | ------------------------------------------------------------------------ 7. In the .trc file: a. Get rid of all comments (lines starting with #) and all other lines not containing output data. Some of this may have to be done manually. b. Adjust the number of spaces at the beginning of each line so it will match that of the Verilog output (.log) file. c. The following output signal values must be translated according to the following table: Change this to this q x r x s z t z u x 8. Run diff on the .trc and .log files using the -i option to make the comparison case insensitive. /im/faust/verify.txt