The full interface chip models are now tested and working.
The full cam chip model has not been tested recently but used
to work; I'll test it as soon as I can.  The revised format for
the cam command is as follows:


Command format for generating .v and .vc files:

   cam arg1 arg2 arg3 . . .

where arg1, arg2, arg3, etc. are items from the
list below.

Arguments may be in any order. Any argument whose first
character is + is passed on to Verilog.
Recognized arguments are:

  xyz
     xyz is a number up to 3 digits long, with the
     digits defined as follows:
       x = number of chips per module (1 - 8)
       y = number of modules per box (1 - 8)
       z = number of boxes (1 - 8)
     trailing ones may be omitted, e.g.,
       12 is equivalent to 121
       4 is equivalent to 411
     modules in the same "box" will be at the same
       level of the interface bus.
     modules in different "boxes" will be at different
       levels of the interface bus.
     Examples:
       411 = one 4 chip module
        13 = three 1 chip modules at same bus level
       113 = three 1 chip modules at different bus levels
     Glue:
       If 4 modules are specified, the glue will be wired
         in a 2 x 2 array in x and y.
       Otherwise, the modules are connected linearly in x.

  B or b = use chip1.edf.v.b for cam model
  +idebug = interface debug on
  +cdebug = cam debug on
  +vectors = cam vector generation on
  +ivectors = interface vector generation on
  +random = generate random Sbus delays
  +noloop = inhibit loop mode
  release, df, or td = subdirectory of /im/cam8/vsim in which
    to find source files.  If not specified, release is assumed.
  grab = include frame grabber
  sram = add sram model to < 4 chip models
  +abort = abort simulation if cam status is X
  lsb0 = connect the lowest order cam chip to pbus data bit 0
         (default)
  lsb4 = connect the lowest order cam chip to pbus data bit 4
  lsb8 = connect the lowest order cam chip to pbus data bit 8
  lsb12 = connect the lowest order cam chip to pbus data bit 12
  +slow = don't kill cam clocks; the default is to kill the cam
          clock on "dead" cycles.
  go = don't check for other Verilog processes before running.
  debugfile.v = filename of debug stuff; the filename must end
                in ".v".  The contents of the debug file will
                be inserted into the end of the system (top
                level) module.
  fullctlsva = include full ctlsvchip (msb)
  fullctlsvb = include full ctlsvchip (lsb)
  fullfsm = include full fsmchip
  fulldataa = include full dataregs (msb)
  fulldatab = include full dataregs (lsb)
  fullcam = include full cam chip

  Note: only one of the "full" options should be specified at a
        time if you want the simulation to fit in memory.

                             Doug