Tom, Ken,
  Some of the hierarchical signal names in the debug
portion of chip1.edf.v produced a problem with the
models which use a full chip (chip.edf.v) for one
of the interface chips.  The problem signal names
begin with "u1.", which indicates indicates the
instance of the cam module, but the signal names
are within the cam module.  Verilog interprets this
correctly when there is only one cam module, but
gets confused when a second cam module (with a 
different instance name, u1054) is included as
part of chip.edf.v.
  The solution is to delete the "u1." portion
of the signal name.  I have done this to the
April 17 version of chip1.edf.v and copied
the result into the release directory.  The
old version is in chip1.edf.v.old.
  This change should be made to future versions
of chip1.edf.v so they will work with the full
chip models.
                        Thanks,
                        Doug