#cell2 * binaryrw txt * 1 any 0 v8r1.5
# "7-Sep-90 GMT" "18:52:09 GMT" "7-Sep-90 GMT" "18:52:09 GMT" dh * .
## This file was created by VLSIvector      #
##  VLSIvector options selected for this file were :
##  AllOutputsTested  TabularOutput  ClockInSim


## Set Aliases  #
set alias l set input low
set alias h set input high
set alias x set input unknown
set alias lz set charged low
set alias hz set charged high
set alias xz set charged unknown
set alias sz set charged *
set alias siv set input vector
set alias scv set charged vector
set alias SEB set external bidirectional
set alias SEI set external input
set alias SEO set external output
set alias echo echo ()

## Set Trace Info                          #
set trace mode tabular
set trace interval 2 2
set option -tabularreportonchange
set output [trc]binaryrw only

###  SET EXTERNAL SIGNALS  ##
SEI  pbclk lsin /clr rs1in rs2in rs3in rs4in ioin
SEO  lsout rs12out io12out rs34out io34out
SEB  din d1out d2out d3out d4out

###  SET EXTERNAL CAPACITANCE  ##



###  WATCH SIGNALS   ###
watch     pbclk lsin /clr rs1in rs2in rs3in rs4in ioin
watch     din d1out d2out d3out d4out lsout rs12out
watch     io12out rs34out io34out

set power high vdd
set power low vss

###   INITIALIZE CLOCKS   ###
set clock pbclk  1(20)  0(20)