#cell2 * chip_1 txt * 4 any 0 v8r1.5
# "15-Jan-91 GMT" "18:48:54 GMT" "15-Jan-91 GMT" "18:48:54 GMT" faust * .
Estimate for chip : chip_1
Estimation Input Parameters :
packagetypes = [ pdip, jpqfp, plcc, llccc, ldccc, sb, ppga, cpga, soic]
libraries = [ vsc10, vsc120, vsc300, vsc320, vgt200, vgt300, vgt350]
chipmiscdata : 
   name                       chip_1
   padload                    50
   coremhz                    20
   padmhz                     10
   inputs                     0
   outputs                    0

Alternative 1

Attribute                     Value
recommended vsss              1
recommended vdds              1
technology                    vsc300
floorplan                     standardCells
density                       core limited (clp)
standard cell area            2553 um squ.
standard cell gates           2129.5
megacell area                 0 um squ.
core x                        2738 microns (108 mils)
core y                        2738 microns (108 mils)
core+pads x                   3631 microns (143 mils)
core+pads y                   3631 microns (143 mils)
core+pads+scribe x            3925 microns (155 mils)
core+pads+scribe y            3925 microns (155 mils)
power                         Low: 83 Typical: 86 High: 89 mW
package 1                     23-10058: 22 pin plastic DIP
package 2                     23-60018: 20 pin plastic leaded chip carrier
package 3                     23-65014: 28 pin leadless ceramic chip carrier
package 4                     23-67514: 28 pin leaded ceramic carrier
package 5                     23-20017: 22 pin ceramic side-brazed package
package 6                     23-80008: 64 pin plastic pin grid array

Alternative 2

Attribute                     Value
recommended vsss              1
recommended vdds              1
technology                    vsc320
floorplan                     standardCells
density                       core limited (clp)
standard cell area            1706 um squ.
standard cell gates           2140
megacell area                 0 um squ.
core x                        1867 microns (74 mils)
core y                        1867 microns (74 mils)
core+pads x                   2760 microns (109 mils)
core+pads y                   2760 microns (109 mils)
core+pads+scribe x            3055 microns (120 mils)
core+pads+scribe y            3055 microns (120 mils)
power                         Low: 29 Typical: 31 High: 33 mW
package 1                     23-10075: 8 pin plastic DIP
package 2                     23-60012: 20 pin plastic leaded chip carrier
package 3                     23-65014: 28 pin leadless ceramic chip carrier
package 4                     23-67514: 28 pin leaded ceramic carrier
package 5                     23-20017: 22 pin ceramic side-brazed package
package 6                     23-80008: 64 pin plastic pin grid array
package 7                     23-15000: 20 pin small outline plastic package

Alternative 3

Attribute                     Value
recommended vsss              1
recommended vdds              1
technology                    vgt300
floorplan                     vgt300030 (1 u vgt300 array) 
core+pads x                   5750 microns (226 mils)
core+pads y                   5750 microns (226 mils)
core+pads+scribe x            6045 microns (238 mils)
core+pads+scribe y            6045 microns (238 mils)
occupancy                     21% of max occupancy 
sites (Cells)                 5754
sites (Blocks)                0
power                         Low: 81 Typical: 84 High: 87 mW
package 1                     23-10093: 24 pin plastic DIP
package 2                     23-61013: 100 pin plastic quad flat package
package 3                     23-60014: 44 pin plastic leaded chip carrier
package 4                     23-65017: 68 pin leadless ceramic chip carrier
package 5                     23-67511: 44 pin leaded ceramic carrier
package 6                     23-20008: 24 pin ceramic side-brazed package
package 7                     23-80004: 84 pin plastic pin grid array
package 8                     23-70048: 68 pin ceramic pin grid array

Alternative 4

Attribute                     Value
recommended vsss              1
recommended vdds              1
technology                    vgt350
floorplan                     vgt300030 (1 u vgt350 array) 
core+pads x                   5750 microns (226 mils)
core+pads y                   5750 microns (226 mils)
core+pads+scribe x            6045 microns (238 mils)
core+pads+scribe y            6045 microns (238 mils)
occupancy                     20% of max occupancy 
sites (Cells)                 5463
sites (Blocks)                0
power                         Low: 82 Typical: 87 High: 91 mW
package 1                     23-10093: 24 pin plastic DIP
package 2                     23-61013: 100 pin plastic quad flat package
package 3                     23-60014: 44 pin plastic leaded chip carrier
package 4                     23-65017: 68 pin leadless ceramic chip carrier
package 5                     23-67511: 44 pin leaded ceramic carrier
package 6                     23-20008: 24 pin ceramic side-brazed package
package 7                     23-80004: 84 pin plastic pin grid array
package 8                     23-70048: 68 pin ceramic pin grid array