# chipc_tv.txt

# ctlsvchip timing verifier command file


# note: you cannot put a comment at the end
#   of a line--the # must be the first character
#   in the line.

# start timing verifier
tv

set prompting off

# load [sim]pred077
load [pst]chip_eval

load chip
set option noblast
set padslimit 2

set stable p54
set stable p55

# sel
set stable p1

# tst
set stable p2


### sbus signals ###

# sb_bg_n (input)
set capacitance 100 p4

# sb_clk (input)
set capacitance 100 p13

# sb_pa [3] (input)
set capacitance 100 p47

# sb_pa [2] (input)
set capacitance 100 p14

# sb_d [15]
set capacitance 100 p27

# sb_d [14]
set capacitance 100 p28

# sb_d [13]
set capacitance 100 p29

# sb_d [12]
set capacitance 100 p30

# sb_d [11]
set capacitance 100 p31

# sb_d [10]
set capacitance 100 p32

# sb_d [9]
set capacitance 100 p33

# sb_d [8]
set capacitance 100 p34

# sb_d [7]
set capacitance 100 p35

# sb_d [6]
set capacitance 100 p36

# sb_d [5]
set capacitance 100 p37

# sb_d [4]
set capacitance 100 p38

# sb_d [3]
set capacitance 100 p39

# sb_d [2]
set capacitance 100 p40

# sb_d [1]
set capacitance 100 p41

# sb_d [0]
set capacitance 100 p42


### pbus signals ###

# pb_clk (input)
set capacitance 100 p26


### interchip signals ###

# zin (input)
set capacitance 40 p3

# partial_xfer (input)
set capacitance 40 p5

# eosi (input)
set capacitance 100 p6

# tmint (input)
set capacitance 40 p7

# op_shift (input)
set capacitance 40 p8

# ldctl (input)
set capacitance 40 p9

# sv_en (input)
set capacitance 40 p10

# donep
set capacitance 40 p11

# hnp_sel (i/o)
set capacitance 40 p12

# sbus_err (input)
set capacitance 40 p15

# incadr (input)
set capacitance 40 p16

# sc [2] (input)
set capacitance 40 p17

# sc [1] (input)
set capacitance 40 p18

# sc [0] (input)
set capacitance 40 p19

# sld (input)
set capacitance 40 p20

# decin (input)
set capacitance 40 p21

# suspend (input)
set capacitance 40 p22

# psd_rc
set capacitance 40 p23

# sync_out
set capacitance 100 p24

# sclr_n (input)
set capacitance 40 p25

# cw_flg8
set capacitance 40 p43

# hw_rd
set capacitance 40 p44

# hstop
set capacitance 20 p45

# od_ri
set capacitance 40 p46

# eofin (input)
set capacitance 100 p48

# incout
set capacitance 40 p49

# sv_ld (input)
set capacitance 40 p50

# int_imm
set capacitance 100 p51

# clr_suspend
set capacitance 40 p52

# imm_sync_in (i/o)
set capacitance 40 p53


#***** delay commands ******
### sbus signals ###

# sb_bg_n (input)
show worst p4

# sb_clk (input)
# show worst p13

# sb_pa [3] (input)
show worst p47

# sb_pa [2] (input)
show worst p14

# sb_d [15]
show delay start p13 end p27

# sb_d [14]
show delay start p13 end p28

# sb_d [13]
show delay start p13 end p29

# sb_d [12]
show delay start p13 end p30

# sb_d [11]
show delay start p13 end p31

# sb_d [10]
show delay start p13 end p32

# sb_d [9]
show delay start p13 end p33

# sb_d [8]
show delay start p13 end p34

# sb_d [7]
show delay start p13 end p35

# sb_d [6]
show delay start p13 end p36

# sb_d [5]
show delay start p13 end p37

# sb_d [4]
show delay start p13 end p38

# sb_d [3]
show delay start p13 end p39

# sb_d [2]
show delay start p13 end p40

# sb_d [1]
show delay start p13 end p41

# sb_d [0]
show delay start p13 end p42


### pbus signals ###

# pb_clk (input)
# show worst p26


### interchip signals ###

# zin (input)
show worst p3

# partial_xfer (input)
show worst p5

# eosi (input)
show worst p6

# tmint (input)
show worst p7

# op_shift (input)
show worst p8

# ldctl (input)
show worst p9

# sv_en (input)
show worst p10

# donep
show delay start p26 end p11

# hnp_sel (i/o)
show delay start p13 end p12
show worst p12

# sbus_err (input)
show worst p15

# incadr (input)
show worst p16
show delay start p16 end u10.u2.u1.u103.u1.u27.d

# sc [2] (input)
show worst p17

# sc [1] (input)
show worst p18

# sc [0] (input)
show worst p19

# sld (input)
show worst p20

# decin (input)
show worst p21

# suspend (input)
show worst p22

# psd_rc
show delay start p26 end p23

# sync_out
show delay start p26 end p24
show delay start p26 end p24 thru U10.U1.U124.U30.u58.i1

# sclr_n (input)
show worst p25

# cw_flg8
show delay start p13 end p43

# hw_rd
show delay start p13 end p44

# hstop
show delay start p13 end p45

# od_ri
# control bit input to opcode reg is
#   not a speed problem
break u10.u2.u2.u64.i1
show delay start p13 end p46

# eofin (input)
show worst p48

# incout
show delay start p13 end p49
show worst (end) p49

# sv_ld (input)
show worst p50

# int_imm
show delay start p13 end p51

# clr_suspend
show delay start p13 end p52

# imm_sync_in (i/o)
show delay start p13 end p53
show worst p53