# chipd_tv.txt

# dataregs timing verifier command file


# note: you cannot put a comment at the end
#   of a line--the # must be the first character
#   in the line.

# start timing verifier 
tv

set prompting off
load [sim]pred077
load chipd
set option noblast
set padslimit 2

set stable p54
set stable p55


### sbus signals ###

# sb_sz [0] (i/o)
set capacitance 100 p4

# sb_bg_n
set capacitance 100 p24

# sb_as
set capacitance 100 p52

# sb_sel (input)
set capacitance 100 p51

# sb_clk (input)
set capacitance 100 p13

# sdh [7]
set capacitance 100 p27

# sdh [6]
set capacitance 100 p28

# sdh [5]
set capacitance 100 p29

# sdh [4]
set capacitance 100 p30

# sdh [3]
set capacitance 100 p31

# sdh [2]
set capacitance 100 p32

# sdh [1]
set capacitance 100 p33

# sdh [0]
set capacitance 100 p34

# sdl [7]
set capacitance 100 p35

# sdl [6]
set capacitance 100 p36

# sdl [5]
set capacitance 100 p37

# sdl [4]
set capacitance 100 p38

# sdl [3]
set capacitance 100 p39

# sdl [2]
set capacitance 100 p40

# sdl [1]
set capacitance 100 p41

# sdl [0]
set capacitance 100 p42


### pbus signals ###

# pb_clk (input)
set capacitance 100 p26

# pd [7] (i/o)
set capacitance 100 p5

# eofin (input)
set capacitance 100 p48

# eofout (input)
set capacitance 100 p50

# pd [6] (i/o)
set capacitance 100 p6

# pd [5] (i/o)
set capacitance 100 p7

# pd [4] (i/o)
set capacitance 100 p8

# pd [3] (i/o)
set capacitance 100 p9

# pd [2] (i/o)
set capacitance 100 p10

# pd [1] (i/o)
set capacitance 100 p11

# pd [0] (i/o)
set capacitance 100 p12


### interchip signals ###

# pc [0] (input)
set capacitance 100 p47

# sdr (input)
set capacitance 100 p14

# sb_sz [1] (i/o)
set capacitance 40 p3

# sld (input)
set capacitance 40 p15

# sc [2] (input)
set capacitance 40 p16

# sc [1] (input)
set capacitance 40 p17

# sc [0] (input)
set capacitance 40 p18

# dr (input)
set capacitance 40 p19

# immed (input)
set capacitance 40 p20

# ps8 (input)
set capacitance 40 p21

# ps16 (input)
set capacitance 40 p22

# pspty (input)
set capacitance 40 p23

# sclr_n (input)
set capacitance 40 p25

# op_data (input)
set capacitance 40 p43

# flg8 (input)
set capacitance 40 p44

# op_shift (input)
set capacitance 40 p45

# pc [1] (input)
set capacitance 40 p46

# sv_sel
set capacitance 40 p49

# ptr_inc (input)
set capacitance 40 p53


#***** delay commands ******


### sbus signals ###

# sb_sz [0] (i/o)
show worst p4
show delay start p13 end p4

# sb_bg_n (input)
show worst p24

# sb_as (input)
show worst p52

# sb_sel (input)
show worst p51

# sb_clk (input)
show worst p13

# sdh [7] (i/o)
show worst p27
show delay start p13 end p27

# sdh [6] (i/o)
show worst p28
show delay start p13 end p28

# sdh [5] (i/o)
show worst p29
show delay start p13 end p29

# sdh [4] (i/o)
show worst p30
show delay start p13 end p30

# sdh [3] (i/o)
show worst p31
show delay start p13 end p31

# sdh [2] (i/o)
show worst p32
show delay start p13 end p32

# sdh [1] (i/o)
show worst p33
show delay start p13 end p33

# sdh [0] (i/o)
show worst p34
show delay start p13 end p34

# sdl [7] (i/o)
show worst p35
show delay start p13 end p35

# sdl [6] (i/o)
show worst p36
show delay start p13 end p36

# sdl [5] (i/o)
show worst p37
show delay start p13 end p37

# sdl [4] (i/o)
show worst p38
show delay start p13 end p38

# sdl [3] (i/o)
show worst p39
show delay start p13 end p39

# sdl [2] (i/o)
show worst p40
show delay start p13 end p40

# sdl [1] (i/o)
show worst p41
show delay start p13 end p41

# sdl [0] (i/o)
show worst p42
show delay start p13 end p42


### pbus signals ###

# pb_clk (input)
show worst p26

# eofin (input)
show worst p48

# eofout (input)
show worst p50

# pd [7] (i/o)
show worst p5
show delay start p13 end p5

# pd [6] (i/o)
show worst p6
show delay start p13 end p6

# pd [5] (i/o)
show worst p7
show delay start p13 end p7

# pd [4] (i/o)
show worst p8
show delay start p13 end p8

# pd [3] (i/o)
show worst p9
show delay start p13 end p9

# pd [2] (i/o)
show worst p10
show delay start p13 end p10

# pd [1] (i/o)
show worst p11
show delay start p13 end p11

# pd [0] (i/o)
show worst p12
show delay start p13 end p12


### interchip signals ###

# pc [0] (input)
show worst p47

# sdr (input)
show worst p14

# sb_sz [1] (i/o)
show worst p3
show delay start p13 end p3

# sld (input)
show worst p15

# sc [2] (input)
show worst p16

# sc [1] (input)
show worst p17

# sc [0] (input)
show worst p18

# dr (input)
show worst p19

# immed (input)
show worst p20

# ps8 (input)
show worst p21

# ps16 (input)
show worst p22

# pspty (input)
show worst p23

# sclr_n (input)
show worst p25

# op_data (input)
show worst p43

# flg8 (input)
show worst p44

# op_shift (input)
show worst p45

# pc [1] (input)
show worst p46

# sv_sel
show delay start p13 end p49

# ptr_inc (input)
show worst p53