# chk_tv.txt

# check critical paths command file

# start timing verifier
tv

set prompting off

load chip
load [pst]chip

# ******************************************************
#      fsmchip
# ******************************************************

set option noblast
set padslimit 2

set stable p54
set stable p55

unbreak u9.*

load [txt]breaku1
load [txt]breaku10
load [txt]breaku8

# set pin capacitances
load [txt]u9_cap

### display delays ###

# ptr_inc
show delay start p2 end p9
show delay start p3 end p9
show delay start p4 end p9

# sdr
show delay start p2 end p11
show delay start p3 end p11
show delay start p4 end p11

# clock
show delay start p13 end u9.u78.u31.sr4.d
show delay start p13 end u9.u78.u81.u6.d


### inputs ###

# sv_on
show worst 2 p7

# sv_sel
show worst 2 p10


# ******************************************************
#      dataregs
# ******************************************************

set option noblast
set padslimit 2

set stable p54
set stable p55

unbreak u8.*
load [txt]breaku1
load [txt]breaku10
load [txt]breaku9


# set pin capacitances
load [txt]u8_cap

#***** delay commands ******

# sb_sel -> sv_on
show delay start p51 end p1
# sb_as -> sv_on
show delay start p52 end p1
# sb_sz[2] -> sv_on
show delay start p2 end p1
# sb_sz[1] -> sv_on
show delay start p3 end p1
# sb_sz[0] -> sv_on
show delay start p4 end p1
# sb_clk -> sv_on
show delay start p13 end p1

# sb_sel -> sv_sel
show delay start p51 end p49
# sb_as -> sv_sel
show delay start p52 end p49
# sb_sz[2] -> sv_sel
show delay start p2 end p49
# sb_sz[1] -> sv_sel
show delay start p3 end p49
# sb_sz[0] -> sv_sel
show delay start p4 end p49
# sv_sel
show delay start p13 end p49

# ptr_inc (input)
show worst p53