#cell2 * ctlchip txt * 2 any 0 v8r1.5
# "13-Jul-90 GMT" "20:18:57 GMT" "13-Jul-90 GMT" "20:18:57 GMT" dh * .
## This file was created by VLSIvector      #
##  VLSIvector options selected for this file were :
##  TabularOutput  ClockInSim


## Set Aliases  #
set alias l set input low
set alias h set input high
set alias x set input unknown
set alias lz set charged low
set alias hz set charged high
set alias xz set charged unknown
set alias sz set charged *
set alias siv set input vector
set alias scv set charged vector
set alias SEB set external bidirectional
set alias SEI set external input
set alias SEO set external output
set alias echo echo ()

## Set Trace Info                          #
set trace interval 2 1
set trace mode tabular
set option -tabularreportonchange
set output [trc]ctlchip only

###  SET EXTERNAL SIGNALS  ##
SEI  sc[2] sc[1] sc[0] sb_d[15] sb_d[14] sb_d[13] sb_d[12] sb_d[11]
SEI  sb_d[10] sb_d[9] sb_d[8] sb_d[7] sb_d[6] sb_d[5] sb_d[4] sb_d[3]
SEI  sb_d[2] sb_d[1] sb_d[0] sclk pclk sld zin tst decin /clr ldctl sel
SEI  psh incadr
SEO  sbdout[15] sbdout[14] sbdout[13] sbdout[12] sbdout[11] sbdout[10]
SEO  sbdout[9] sbdout[8] sbdout[7] sbdout[6] sbdout[5] sbdout[4]
SEO  sbdout[3] sbdout[2] sbdout[1] sbdout[0] donep decout wr_flg8
SEO  in_imm hw_cw np_hj incout opdata pseldone

###  SET EXTERNAL CAPACITANCE  ##


###  DEFINE VECTORS    ##
vector sc[2:0] sc[2] sc[1] sc[0]
vector sb_d[15:0] sb_d[15] sb_d[14] sb_d[13] sb_d[12] sb_d[11] sb_d[10] -
 sb_d[9] sb_d[8] sb_d[7] sb_d[6] sb_d[5] sb_d[4] sb_d[3] sb_d[2] -
 sb_d[1] sb_d[0]
vector sbdout[15:0] sbdout[15] sbdout[14] sbdout[13] sbdout[12] -
 sbdout[11] sbdout[10] sbdout[9] sbdout[8] sbdout[7] sbdout[6] -
 sbdout[5] sbdout[4] sbdout[3] sbdout[2] sbdout[1] sbdout[0]

###  WATCH SIGNALS   ###
watch sclk pclk /clr decin ldctl incadr psh sld sc sb_d
watch donep decout wr_flg8 in_imm hw_cw np_hj incout opdata pseldone sbdout


set power high vdd
set power low vss

###   INITIALIZE CLOCKS   ###
set clock sclk  1(25)  0(25)
set clock pclk  1(20)  0(30)