#cell2 * datain txt * 4 any 0 v8r1.5
# "9-Jul-90 GMT" "19:39:26 GMT" "9-Jul-90 GMT" "19:39:26 GMT" dh * .
## This file was created by VLSIvector      #
##  VLSIvector options selected for this file were :
##  TabularOutput  ClockInSim


## Set Aliases  #
set alias l set input low
set alias h set input high
set alias x set input unknown
set alias lz set charged low
set alias hz set charged high
set alias xz set charged unknown
set alias sz set charged *
set alias siv set input vector
set alias scv set charged vector
set alias SEB set external bidirectional
set alias SEI set external input
set alias SEO set external output
set alias echo echo ()

## Set Trace Info                          #
set trace interval 2 1
set trace mode tabular
set option -tabularreportonchange
set output [trc]datain only

###  SET EXTERNAL SIGNALS  ##
SEI  sc[2] sc[1] sc[0] pc[1] pc[0] sb_dh[7] sb_dh[6] sb_dh[5] sb_dh[4]
SEI  sb_dh[3] sb_dh[2] sb_dh[1] sb_dh[0] sb_dl[7] sb_dl[6] sb_dl[5]
SEI  sb_dl[4] sb_dl[3] sb_dl[2] sb_dl[1] sb_dl[0] pb_di[7] pb_di[6]
SEI  pb_di[5] pb_di[4] pb_di[3] pb_di[2] pb_di[1] pb_di[0] sb_clk
SEI  pb_clk /rst immed sld pdrdata pdr2 drpty drop opin eofin eofout
SEI  pcwr
SEO  pb_d[7] pb_d[6] pb_d[5] pb_d[4] pb_d[3] pb_d[2] pb_d[1] pb_d[0]
SEO  pdav

###  SET EXTERNAL CAPACITANCE  ##


###  DEFINE VECTORS    ##
vector sc[2:0] sc[2] sc[1] sc[0]
vector pc[1:0] pc[1] pc[0]
vector sb_dh[7:0] sb_dh[7] sb_dh[6] sb_dh[5] sb_dh[4] sb_dh[3] sb_dh[2] -
 sb_dh[1] sb_dh[0]
vector sb_dl[7:0] sb_dl[7] sb_dl[6] sb_dl[5] sb_dl[4] sb_dl[3] sb_dl[2] -
 sb_dl[1] sb_dl[0]
vector pb_d[7:0] pb_d[7] pb_d[6] pb_d[5] pb_d[4] pb_d[3] pb_d[2] -
 pb_d[1] pb_d[0]
vector pb_di[7:0] pb_di[7] pb_di[6] pb_di[5] pb_di[4] pb_di[3] pb_di[2] -
 pb_di[1] pb_di[0]

###  WATCH SIGNALS   ###
watch sb_clk pb_clk sc pc /rst immed sld pdrdata pdr2 drpty drop opin eofin
watch eofout pcwr pdav sb_dh sb_dl pb_d pb_di

set power high vdd
set power low vss

###   INITIALIZE CLOCKS   ###
set clock sb_clk  1(25)  0(25)
set clock pb_clk  1(20)  0(30)