#cell2 * ivec txt * 1 any 0 v8r2.2
# "6-Aug-91 GMT" "16:38:19 GMT" "6-Aug-91 GMT" "16:38:19 GMT" faust * .

VLSIsim v8r2 changes:
   1. Tristate transitions (such as 1 --> 1z) are now reported
      in the trace output like any other changes and will trigger
      tabular output.  To disable this feature use "set option
      -reportZChanges".
   2. In dynamic trace output, vectors are now reported as they
      change, just like nodes.  To disable this feature, use
      "set option -dynamicVectors".
   3. Charge decay:  tristated nodes go unknown after a specified
      interval, set by "set simparms chargeDecayTime".
      Option reportZChanges must be on for this to work.
   4. More accurate delays for parallel logic gates:  Previously
      the entire delay was reduced in proportion to the number of
      drivers; now only load-dependent part of delay is so reduced.
  Reading command file '/cam/vlsi/v8r2/etc/cmn12.sim'
# Using VLSI CMOS CMN12 calibration, 11/27/89.  WORST CASE SPEED
# Individual transistor calibrations were done at Vdd=4.65V, Vss=0.1V,
# T=70 degrees C.  Delays of instances of transistors in your netlist will
# reflect this characterized operating point.  Delays for instances of
# cells/macros use the values in the models located in the associated
# libraries on your search path.
# Note: default interconnect capacitance is the same as CMN20A: 0.01pF.
  Time = 0:0   [0 ns]
VLSIsim>

TERMINATING SIMULATION


VLSIsim v8r2 changes:
   1. Tristate transitions (such as 1 --> 1z) are now reported
      in the trace output like any other changes and will trigger
      tabular output.  To disable this feature use "set option
      -reportZChanges".
   2. In dynamic trace output, vectors are now reported as they
      change, just like nodes.  To disable this feature, use
      "set option -dynamicVectors".
   3. Charge decay:  tristated nodes go unknown after a specified
      interval, set by "set simparms chargeDecayTime".
      Option reportZChanges must be on for this to work.
   4. More accurate delays for parallel logic gates:  Previously
      the entire delay was reduced in proportion to the number of
      drivers; now only load-dependent part of delay is so reduced.
  Reading command file '/cam/vlsi/v8r2/etc/cmn12.sim'
# Using VLSI CMOS CMN12 calibration, 11/27/89.  WORST CASE SPEED
# Individual transistor calibrations were done at Vdd=4.65V, Vss=0.1V,
# T=70 degrees C.  Delays of instances of transistors in your netlist will
# reflect this characterized operating point.  Delays for instances of
# cells/macros use the values in the models located in the associated
# libraries on your search path.
# Note: default interconnect capacitance is the same as CMN20A: 0.01pF.
  Time = 0:0   [0 ns]
LOAD [la]sys1 ""
  Redefining vector: U2.U10.U2.U1.r0
  Redefining vector: U5.U10.U2.U1.r0
  Redefining vector: U4.U10.U2.U1.r0
  Redefining vector: U1.U10.U2.U1.r0
  Redefining vector: U3.U10.U2.U1.r0
  There are 13918 nodes, 5240 gates, 5490 instances, 15 transistors.
  Time = 0:0   [0 ns]
VLSIsim>

TERMINATING SIMULATION

sb_d[31]
sb_d[30]
sb_d[29]
sb_d[28]
sb_d[27]
sb_d[26]
sb_d[25]
sb_d[24]
sb_d[23]
sb_d[22]
sb_d[21]
sb_d[20]
sb_d[19]
sb_d[18]
sb_d[17]
sb_d[16]
sb_d[15]
sb_d[14]
sb_d[13]
sb_d[12]
sb_d[11]
sb_d[10]
sb_d[9]
sb_d[8]
sb_d[7]
sb_d[6]
sb_d[5]
sb_d[4]
sb_d[3]
sb_d[2]
sb_d[1]
sb_d[0]
sb_ack_[2]
sb_ack_[1]
sb_ack_[0]
sb_siz[2]
sb_siz[1]
sb_siz[0]
pb_d[15]
pb_d[14]
pb_d[13]
pb_d[12]
pb_d[11]
pb_d[10]
pb_d[9] sb_d[31]
sb_d[30]
sb_d[29]
sb_d[28]
sb_d[27]
sb_d[26]
sb_d[25]
sb_d[24]
sb_d[23]
sb_d[22]
sb_d[21]
sb_d[20]
sb_d[19]
sb_d[18]
sb_d[17]
sb_d[16]
sb_d[15]
sb_d[14]
sb_d[13]
sb_d[12]
sb_d[11]
sb_d[10]
sb_d[9]
sb_d[8]
sb_d[7]
sb_d[6]
sb_d[5]
sb_d[4]
sb_d[3]
sb_d[2]
sb_d[1]
sb_d[0]
sb_ack_[2]
sb_ack_[1]
sb_ack_[0]
sb_siz[2]
sb_siz[1]
sb_siz[0]
pb_d[15]
pb_d[14]
pb_d[13]
pb_d[12]
pb_d[11]
pb_d[10]
pb_d[9]
pb_d[8]
pb_d[7]
pb_d[6]
pb_d[5]
pb_d[4]
pb_d[3]
pb_d[2]
pb_d[1]
pb_d[0]
sb_rd
sb_clk
pb_clk
sb_pa16
sb_pa3
sb_pa2
sb_bg_1
sb_merr_
sb_sel_1
sb_reset_n
sb_as_
pb_eofin
pb_eosi
sb_irq_1
sb_br_1
pb_iosel
pb_eofout
pb_rst_
pb_sync

pb_d[8]
pb_d[7]
pb_d[6]
pb_d[5]
pb_d[4]
pb_d[3]
pb_d[2]
pb_d[1]
pb_d[0]
sb_rd
sb_clk
pb_clk
sb_pa16
sb_pa3
sb_pa2
sb_bg_1
sb_merr_
sb_sel_1
sb_reset_n
sb_as_
pb_eofin
pb_eosi
sb_irq_1
sb_br_1
pb_iosel
pb_eofout
pb_rst_
pb_sync