qsim
set simparms transistorDelay 10
set simparms timescale 100
set simparms delayFactor 1.00
set radix 16
node dummy
set clock (report) dummy 0(14); 1(40) 0
set chipparms u1.u8.* ; suhDelayFactor 0
set chipparms u1.u9.* ; suhDelayFactor 0
set chipparms u2.u8.* ; suhDelayFactor 0
set chipparms u2.u9.* ; suhDelayFactor 0
set chipparms u3.u8.* ; suhDelayFactor 0
set chipparms u3.u10.* ; suhDelayFactor 0
set chipparms u4.u9.* ; suhDelayFactor 0
set chipparms u4.u10.* ; suhDelayFactor 0
set chipparms u5.u9.* ; suhDelayFactor 0
set chipparms u5.u10.* ; suhDelayFactor 0

set switch chip350nle
load [nls]sys2
# load [pst]sys2
load [txt]sys1_cap
set options tab
set trace interval 1
set forced low u1.pb_clk_d
set forced high u1.sb_clk_n_d
set forced low u1.sclr_n_d
set forced low u2.pb_clk_d
set forced high u2.sb_clk_n_d
set forced low u2.sclr_n_d
set forced low u3.pb_clk_d
set forced high u3.sb_clk_n_d
set forced low u3.sclr_n_d
set forced high u1.pb_clk_n_f
set forced high u1.sb_clk_n_f
set forced low u1.u9.u4.sclr_n
set forced high u2.pb_clk_n_f
set forced high u2.sb_clk_n_f
set forced low u2.u9.u4.sclr_n
set forced high u4.pb_clk_n_f
set forced high u4.sb_clk_n_f
set forced low u4.u9.u4.sclr_n
set forced high u5.pb_clk_n_f
set forced high u5.sb_clk_n_f
set forced low u5.u9.u4.sclr_n
set forced low u3.pb_clk_c
set forced low u3.sb_clk_c
set forced low u3.sclr_n_c
set forced low u4.pb_clk_c
set forced low u4.sb_clk_c
set forced low u4.sclr_n_c
set forced low u5.pb_clk_c
set forced low u5.sb_clk_c
set forced low u5.sclr_n_c

load [sim]ivec
quit
quit
