qsim
set simparms transistorDelay 10
set simparms timescale 100
set simparms delayFactor .99
set radix 16
node dummy
set clock (report) dummy 0(14); 1(40) 0
set switch chipnle
load [la]sys2
load [txt]sys1_cap
set options tab
set trace interval 1
set forced low u1.u8.pb_clk
set forced high u1.u8.sb_clk_n
set forced low u1.u8.sclr_n
set forced low u2.u8.pb_clk
set forced high u2.u8.sb_clk_n
set forced low u2.u8.sclr_n
set forced low u3.u8.pb_clk
set forced high u3.u8.sb_clk_n
set forced low u3.u8.sclr_n
set forced high u1.u9.pb_clk_n
set forced high u1.u9.sb_clk_n
set forced low u1.u9.u4.sclr_n
set forced high u2.u9.pb_clk_n
set forced high u2.u9.sb_clk_n
set forced low u2.u9.u4.sclr_n
set forced high u4.u9.pb_clk_n
set forced high u4.u9.sb_clk_n
set forced low u4.u9.u4.sclr_n
set forced high u5.u9.pb_clk_n
set forced high u5.u9.sb_clk_n
set forced low u5.u9.u4.sclr_n
set forced low u3.u10.pb_clk
set forced low u3.u10.sb_clk
set forced low u3.u10.sclr_n
set forced low u4.u10.pb_clk
set forced low u4.u10.sb_clk
set forced low u4.u10.sclr_n
set forced low u5.u10.pb_clk
set forced low u5.u10.sb_clk
set forced low u5.u10.sclr_n
load [sim]ivec1
quit
quit
