#cell2 * slavereg txt * 2 any 0 v8r1.5
# "11-Jul-90 GMT" "20:57:32 GMT" "11-Jul-90 GMT" "20:57:32 GMT" dh * .
## This file was created by VLSIvector      #
##  VLSIvector options selected for this file were :
##  TabularOutput  ClockInSim


## Set Aliases  #
set alias l set input low
set alias h set input high
set alias x set input unknown
set alias lz set charged low
set alias hz set charged high
set alias xz set charged unknown
set alias sz set charged *
set alias siv set input vector
set alias scv set charged vector
set alias SEB set external bidirectional
set alias SEI set external input
set alias SEO set external output
set alias echo echo ()

## Set Trace Info                          #
set trace interval 2 1
set trace mode tabular
set option -tabularreportonchange
set output [trc]slavereg only

###  SET EXTERNAL SIGNALS  ##
SEI  sva[1] sva[0] sbdin[15] sbdin[14] sbdin[13] sbdin[12] sbdin[11]
SEI  sbdin[10] sbdin[9] sbdin[8] sbdin[7] sbdin[6] sbdin[5] sbdin[4]
SEI  sbdin[3] sbdin[2] sbdin[1] sbdin[0] sb_clk ldptr drhnp svld svdr
SEI  /clr tmint sbint camint sfint sb_rst
SEO  sbdout[15] sbdout[14] sbdout[13] sbdout[12] sbdout[11] sbdout[10]
SEO  sbdout[9] sbdout[8] sbdout[7] sbdout[6] sbdout[5] sbdout[4]
SEO  sbdout[3] sbdout[2] sbdout[1] sbdout[0] hok /rstcam drint /rstint
SEO  tmcmint svsel

###  SET EXTERNAL CAPACITANCE  ##


###  DEFINE VECTORS    ##
vector sva[1:0] sva[1] sva[0]
vector sbdin[15:0] sbdin[15] sbdin[14] sbdin[13] sbdin[12] sbdin[11] -
 sbdin[10] sbdin[9] sbdin[8] sbdin[7] sbdin[6] sbdin[5] sbdin[4] -
 sbdin[3] sbdin[2] sbdin[1] sbdin[0]
vector sbdout[15:0] sbdout[15] sbdout[14] sbdout[13] sbdout[12] -
 sbdout[11] sbdout[10] sbdout[9] sbdout[8] sbdout[7] sbdout[6] -
 sbdout[5] sbdout[4] sbdout[3] sbdout[2] sbdout[1] sbdout[0]

###  WATCH SIGNALS   ###
watch sb_clk /clr ldptr drhnp tmint sbint camint sfint sb_rst
watch sva svld svdr sbdin hok sbdout /rstcam drint /rstint tmcmint svsel


set power high vdd
set power low vss

###   INITIALIZE CLOCKS   ###
set clock sb_clk  1(25)  0(25)