sv_on: VLSItv> show delay start p2 end p1 Rising Output: 14.5ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P2 .0[.0] input .0[.0] 100.00 THRU U542.C .1[.1] pt6o12: .1[.1] .68 U550.IN=tst_c 2.2[1.2] lstc00: 2.7[1.1] 7.31 U8.U13.U3.ZN 4.8[2.9] nr03d1: 2.6[1.7] .61 U8.U13.U4.Z 6.1[3.3] an04d1: 1.3[.5] .32 U8.U13.U15.Z=sv_- on_d 7.1[3.5] ni01d5: 1.0[.2] .88 U541.Z 10.1[5.6] mx41d1: 3.0[2.1] 2.16 END U1057.PAD=P1 14.5[8.7] pt6o41: 4.4[3.1] 30.00 Falling Output: 15.7ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P2 .0[.0] input .0[.0] 100.00 THRU U542.C .1[.1] pt6o12: .1[.1] .68 U550.IN=tst_c 2.8[2.3] lstc00: 2.7[2.2] 7.31 U8.U13.U3.ZN 3.8[2.8] nr03d1: 1.0[.5] .61 U8.U13.U4.Z 4.7[2.9] an04d1: .9[.1] .32 U8.U13.U15.Z=sv_- on_d 6.0[3.0] ni01d5: 1.3[.1] .88 U541.Z 9.0[5.0] mx41d1: 3.0[2.0] 2.16 END U1057.PAD=P1 15.7[9.3] pt6o41: 6.7[4.3] 30.00 VLSItv> VLSItv> sh wor 1 p7 Rising Output: r1 5.8ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P7 .0[.0] input .0[.0] 40.00 THRU U895.C .1[.1] pc6o12: .1[.1] .47 U591.IN=tmint_c 1.6[1.0] lscc00: 1.5[1.0] 4.90 U9.U78.U31.u5.ZN 2.2[1.4] in01d1: .6[.4] .42 U9.U78.U31.u6.ZN 4.4[3.0] nd03d1: 2.2[1.6] .86 END U9.U78.U31.u16.ZN 5.8[3.4] oa05d1: 1.4[.4] .40 Falling Output: f1 6.0ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P7 .0[.0] input .0[.0] 40.00 THRU U895.C .1[.1] pc6o12: .1[.1] .47 U591.IN=tmint_c 1.6[1.0] lscc00: 1.5[1.0] 4.90 U9.U78.U31.u5.ZN 2.2[1.4] in01d1: .6[.4] .42 U9.U78.U31.u25.ZN 2.9[1.6] nr03d1: .7[.2] .35 U9.U78.U31.u14.ZN 4.4[2.4] oa04d1: 1.5[.8] .45 U9.U78.U31.u26.ZN 4.7[2.6] in01d1: .3[.2] .30 END U9.U78.U31.u27.Z 6.0[2.7] or02d1: 1.2[.1] .31 sv_sel: VLSItv> show delay start p52 end p49 Rising Output: 15.7ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P52 .0[.0] input .0[.0] 100.00 THRU U1269.C .1[.1] pt6o13: .1[.1] .71 U994.IN=sb_as_d 1.7[.7] lstc00: 1.6[.6] 4.08 U8.U13.U10.ZN 2.8[1.7] in01d1: 1.2[1.0] .81 U8.U13.U9.Z 4.2[2.1] an03d1: 1.3[.4] .40 U8.U13.U14.Z=sv_- sel_d 5.2[2.3] ni01d5: 1.0[.2] 1.05 U1090.Z 6.8[3.0] mx41d1: 1.7[.7] .82 END U757.PAD=P49 15.7[9.7] pc6o11: 8.9[6.7] 30.00 Falling Output: 12.0ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P52 .0[.0] input .0[.0] 100.00 THRU U1269.C .1[.1] pt6o13: .1[.1] .71 U994.IN=sb_as_d 1.8[1.3] lstc00: 1.7[1.2] 4.08 U8.U13.U10.ZN 2.6[1.9] in01d1: .8[.7] .81 U8.U13.U9.Z 3.7[2.2] an03d1: 1.1[.2] .40 U8.U13.U14.Z=sv_- sel_d 5.1[2.3] ni01d5: 1.3[.1] 1.05 U1090.Z 6.8[3.0] mx41d1: 1.7[.7] .82 END U757.PAD=P49 12.0[6.0] pc6o11: 5.2[3.0] 30.00 VLSItv> sh wor 1 p10 Rising Output: r1 5.9ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P10 .0[.0] input .0[.0] 40.00 THRU U899.C .1[.1] pc6o12: .1[.1] .46 U614.IN=sv_en_c 2.1[1.5] lscc00: 2.0[1.5] 7.30 U9.U78.U31.u6.ZN 3.4[2.4] nd03d1: 1.3[.9] .86 U9.U78.U31.u10.ZN 4.7[2.9] nd04d1: 1.2[.4] .35 END U9.U78.U42.ZN 5.9[3.6] nr02d1: 1.2[.8] .39 Falling Output: f1 5.4ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P10 .0[.0] input .0[.0] 40.00 THRU U899.C .1[.1] pc6o12: .1[.1] .46 U614.IN=sv_en_c 1.9[1.5] lscc00: 1.8[1.5] 7.30 U9.U78.U31.u6.ZN 4.1[3.1] nd03d1: 2.2[1.6] .86 U9.U78.U31.u10.ZN 4.7[3.3] nd04d1: .6[.2] .35 END U9.U78.U42.ZN 5.4[3.5] nr02d1: .7[.3] .39 clock delay in fsmchip: VLSItv> sh del start p13 end u9.u78.u81.u6.cp Rising Output: 3.5ns. cumulative individual nodeName delay[wire delay] component delay[wire] cap ----------- ---------------------- ---------- ----------- ------- START P13 .0[.0] input .0[.0] 100.00 THRU U1059.C .4[.4] pc6d00: .4[.4] 2.85 U638.IN=sb_clk_a- ux 1.5[1.0] lstc00: 1.1[.6] 2.25 U1113.ZN=sb_clk_- n_f 2.3[1.7] in01d5: .8[.7] 3.78 END U9.U80.ZN 3.5[2.7] in01d5: 1.2[1.1] 3.55