# sys1_cap.txt

# command file to set capacitances in sys1, the
#   vlsi interface board model


# note: you cannot put a comment at the end
#   of a line--the # must be the first character
#   in the line.

###
# ctlsvchip
###

### sbus signals ###

# sb_d [15]
set capacitance 100 u1.p27
set capacitance 100 u2.p27

# sb_d [14]
set capacitance 100 u1.p28
set capacitance 100 u2.p28

# sb_d [13]
set capacitance 100 u1.p29
set capacitance 100 u2.p29

# sb_d [12]
set capacitance 100 u1.p30
set capacitance 100 u2.p30

# sb_d [11]
set capacitance 100 u1.p31
set capacitance 100 u2.p31

# sb_d [10]
set capacitance 100 u1.p32
set capacitance 100 u2.p32

# sb_d [9]
set capacitance 100 u1.p33
set capacitance 100 u2.p33

# sb_d [8]
set capacitance 100 u1.p34
set capacitance 100 u2.p34

# sb_d [7]
set capacitance 100 u1.p35
set capacitance 100 u2.p35

# sb_d [6]
set capacitance 100 u1.p36
set capacitance 100 u2.p36

# sb_d [5]
set capacitance 100 u1.p37
set capacitance 100 u2.p37

# sb_d [4]
set capacitance 100 u1.p38
set capacitance 100 u2.p38

# sb_d [3]
set capacitance 100 u1.p39
set capacitance 100 u2.p39

# sb_d [2]
set capacitance 100 u1.p40
set capacitance 100 u2.p40

# sb_d [1]
set capacitance 100 u1.p41
set capacitance 100 u2.p41

# sb_d [0]
set capacitance 100 u1.p42
set capacitance 100 u2.p42


### interchip signals ###

# donep
# %debug reduced 30 -> 0 5/20/92 NOT!
set capacitance 30 u1.p11

# pdec_0
set capacitance 30 u2.p11

# hnp_sel (i/o)
set capacitance 40 u1.p12
# set capacitance 40 u2.p12

# suspend (input)
set capacitance 40 u1.p22
# set capacitance 40 u2.p22

# psd_rc
set capacitance 100 u1.p23
set capacitance 40 u2.p23

# sync_out
set capacitance 100 u1.p24
set capacitance 100 u2.p24

# cw_flg8
set capacitance 40 u1.p43
set capacitance 40 u2.p43

# hw_rd
set capacitance 40 u1.p44
# p_rd
set capacitance 40 u2.p44

# hstop
set capacitance 40 u1.p45
set capacitance 40 u2.p45

# od_ri
# op_data
set capacitance 40 u1.p46
# ifc_rst_n
set capacitance 40 u2.p46

# incout
#  reduced to help timing
# set capacitance 40 u1.p49
# set capacitance 40 u2.p49
set capacitance 40 u1.p49
set capacitance 40 u2.p49

# int_imm
set capacitance 100 u1.p51
set capacitance 100 u2.p51

# clr_suspend
set capacitance 40 u1.p52
set capacitance 40 u2.p52

# imm_sync_in (i/o)
set capacitance 40 u1.p53
set capacitance 40 u2.p53


###
# fsmchip
###

### sbus signals ###

# ack[2]
set capacitance 100 u3.p2

# ack[1]
set capacitance 100 u3.p3

# ack[0]
set capacitance 100 u3.p4

# sb_br
set capacitance 100 u3.p27

# sb_rd
set capacitance 100 u3.p52



### pbus signals ###

# eofin
set capacitance 100 u3.p12

# eofout
set capacitance 100 u3.p23

# iosel
set capacitance 100 u3.p24


### interchip signals ###

# hstop
set capacitance 20 u3.p15

# prom_dr_n
set capacitance 40 u3.p22

# param_dr_n
set capacitance 40 u3.p5

# eosi
set capacitance 40 u3.p6

# sc[2]
set capacitance 80 u3.p31

# sc[1]
set capacitance 80 u3.p32

# sc[0]
set capacitance 80 u3.p33

# pc[1]
set capacitance 40 u3.p45

# pc[0]
set capacitance 40 u3.p46

# tmint
set capacitance 30 u3.p47

# sv_ld
set capacitance 40 u3.p48


# incadr
set capacitance 40 u3.p34

# sld
set capacitance 40 u3.p30

# sbus_err
set capacitance 100 u3.p35

# ps16
set capacitance 40 u3.p42

# ps8
set capacitance 40 u3.p43

# dr
set capacitance 40 u3.p44

# pspty
set capacitance 40 u3.p41

# pcwr
set capacitance 10 u3.p40

# pldec
set capacitance 40 u3.p39

# ldctl
set capacitance 40 u3.p37

# sv_en
#   reduced to help timing 5/5/92 NOT!
# set capacitance 30 u3.p36
set capacitance 40 u3.p36

# sv_on
# %debug
# set capacitance 30 u3.p7
set capacitance 30 u3.p7

# op_shift
set capacitance 40 u3.p8

# ptr_inc
# %debug reduced 40 -> 30 5/17/92
set capacitance 30 u3.p9

# sv_sel
set capacitance 40 u3.p10

# sdr
# %debug reduced 40 -> 30 5/17/92 NOT!
set capacitance 40 u3.p11

# cw
set capacitance 40 u3.p29

# sclr_n
#  changed for simulation
# set capacitance 50 u3.p50
set capacitance 60 u3.p50

# partial_xfer
set capacitance 40 u3.p51


### inputs ###

# rd
set capacitance 10 u3.p49

# pdav
set capacitance 10 u3.p18


###
# dataregs
###

### sbus signals ###

# sb_sz [0] (i/o)
set capacitance 100 u4.p4
set capacitance 100 u5.p4

# sb_bg_n
set capacitance 100 u4.p24
set capacitance 100 u5.p24

# sb_as
set capacitance 100 u4.p52
set capacitance 100 u5.p52

# sdh [7]
set capacitance 100 u4.p27
set capacitance 100 u5.p27

# sdh [6]
set capacitance 100 u4.p28
set capacitance 100 u5.p28

# sdh [5]
set capacitance 100 u4.p29
set capacitance 100 u5.p29

# sdh [4]
set capacitance 100 u4.p30
set capacitance 100 u5.p30

# sdh [3]
set capacitance 100 u4.p31
set capacitance 100 u5.p31

# sdh [2]
set capacitance 100 u4.p32
set capacitance 100 u5.p32

# sdh [1]
set capacitance 100 u4.p33
set capacitance 100 u5.p33

# sdh [0]
set capacitance 100 u4.p34
set capacitance 100 u5.p34

# sdl [7]
set capacitance 100 u4.p35
set capacitance 100 u5.p35

# sdl [6]
set capacitance 100 u4.p36
set capacitance 100 u5.p36

# sdl [5]
set capacitance 100 u4.p37
set capacitance 100 u5.p37

# sdl [4]
set capacitance 100 u4.p38
set capacitance 100 u5.p38

# sdl [3]
set capacitance 100 u4.p39
set capacitance 100 u5.p39

# sdl [2]
set capacitance 100 u4.p40
set capacitance 100 u5.p40

# sdl [1]
set capacitance 100 u4.p41
set capacitance 100 u5.p41

# sdl [0]
set capacitance 100 u4.p42
set capacitance 100 u5.p42


### pbus signals ###

# pd [7] (i/o)
set capacitance 100 u4.p5
set capacitance 100 u5.p5

# pd [6] (i/o)
set capacitance 100 u4.p6
set capacitance 100 u5.p6

# pd [5] (i/o)
set capacitance 100 u4.p7
set capacitance 100 u5.p7

# pd [4] (i/o)
set capacitance 100 u4.p8
set capacitance 100 u5.p8

# pd [3] (i/o)
set capacitance 100 u4.p9
set capacitance 100 u5.p9

# pd [2] (i/o)
set capacitance 100 u4.p10
set capacitance 100 u5.p10

# pd [1] (i/o)
set capacitance 100 u4.p11
set capacitance 100 u5.p11

# pd [0] (i/o)
set capacitance 100 u4.p12
set capacitance 100 u5.p12


### interchip signals ###

# sb_sz [1] (i/o)
set capacitance 40 u4.p3
set capacitance 40 u5.p3