# u10_del.txt

# delay commands for ctlsvchip

# ******************************************************
#      ctlsvchip
# ******************************************************

set option noblast
set padslimit 2

set stable p54
set stable p55

# sel
set stable p1

# tst
set stable p2

unbreak u10.*

load [txt]breaku1
load [txt]breaku9
load [txt]breaku8

# set pin capacitances
load [txt]u10_cap


#***** delay commands ******
### sbus signals ###

# sb_bg_n (input)
show worst 2 p4

# sb_clk (input)
show worst 2 p13

# sb_pa [3] (input)
show worst 2 p47

# sb_pa [2] (input)
show worst 2 p14

# sb_d [15]
show delay start p13 end p27 

# sb_d [14]
show delay start p13 end p28 

# sb_d [13]
show delay start p13 end p29 

# sb_d [12]
show delay start p13 end p30 

# sb_d [11]
show delay start p13 end p31 

# sb_d [10]
show delay start p13 end p32 

# sb_d [9]
show delay start p13 end p33 

# sb_d [8]
show delay start p13 end p34 

# sb_d [7]
show delay start p13 end p35 

# sb_d [6]
show delay start p13 end p36 

# sb_d [5]
show delay start p13 end p37 

# sb_d [4]
show delay start p13 end p38 

# sb_d [3]
show delay start p13 end p39 

# sb_d [2]
show delay start p13 end p40 

# sb_d [1]
show delay start p13 end p41 

# sb_d [0]
show delay start p13 end p42 


### interchip signals ###

# zin (input)
show worst 2 p3

# partial_xfer (input)
show worst 2 p5

# eosi (input)
show worst 2 p6

# tmint (input)
show worst 2 p7

# op_shift (input)
show worst 2 p8

# ldctl (input)
show worst 2 p9

# sv_en (input)
show worst 2 p10

# donep
show delay start p26 end p11

# hnp_sel (i/o)
show delay start p13 end p12 
show worst 2 p12

# sbus_err (input)
show worst 2 p15

# incadr (input)
show worst 2 p16
show delay start p16 end u10.u2.u1.u103.u1.u27.d

# sc [2] (input)
show worst 2 p17

# sc [1] (input)
show worst 2 p18

# sc [0] (input)
show worst 2 p19

# sld (input)
show worst 2 p20

# decin (input)
show worst 2 p21

# suspend (input)
show worst 2 p22

# psd_rc
show delay start p26 end p23

# sync_out
show delay start p26 end p24
show delay start p26 end p24 thru U10.U1.U124.U30.u58.i1

# sclr_n (input)
show worst 2 p25

# cw_flg8
show delay start p13 end p43 

# hw_rd
show delay start p13 end p44 

# hstop
show delay start p13 end p45 

# od_ri
# control bit input to opcode reg is
#   not a speed problem
break u10.u2.u2.u64.i1
show delay start p13 end p46 

# eofin (input)
show worst 2 p48

# incout
break u10.u2.u1.u103.u1.u70.zn  u10.u2.u1.u103.u55.a1
show delay start p13 end p49 
show worst 2 (end) p49
unbreak u10.u2.u1.u103.u1.ones  u10.u2.u1.u103.u55.a1

# sv_ld (input)
show worst 2 p50

# int_imm
show delay start p13 end p51 
show delay start p13 end p51  thru u10.u19.u8.z

# clr_suspend
show delay start p13 end p52 

# imm_sync_in (i/o)
show delay start p13 end p53 
show worst 2 p53