# chip_tv.txt

# complete chip timing verifier command file


# note: you cannot put a comment at the end
#   of a line--the # must be the first character
#   in the line.

# start timing verifier
tv

set prompting off


# comment these out if using .pst file
# load [sim]pred077
load chip

# comment these out if using .predcap file
# load chip
load [pst]chip


# break all paths to/from the cam chip
set break u1054.evc_data
set break u1054.glue_en_n[5]
set break u1054.glue_en_n[4]
set break u1054.glue_en_n[3]
set break u1054.glue_en_n[2]
set break u1054.glue_en_n[1]
set break u1054.glue_en_n[0]
set break u1054.glue_out[5]
set break u1054.glue_out[4]
set break u1054.glue_out[3]
set break u1054.glue_out[2]
set break u1054.glue_out[1]
set break u1054.glue_out[0]
set break u1054.da[11]
set break u1054.da[10]
set break u1054.da[9]
set break u1054.da[8]
set break u1054.da[7]
set break u1054.da[6]
set break u1054.da[5]
set break u1054.da[4]
set break u1054.da[3]
set break u1054.da[2]
set break u1054.da[1]
set break u1054.da[0]
set break u1054.ddout[3]
set break u1054.ddout[2]
set break u1054.ddout[1]
set break u1054.ddout[0]
set break u1054.dras_n
set break u1054.dcas_n
set break u1054.dwe_n
set break u1054.doe_n
set break u1054.fly_out
set break u1054.disp_out
set break u1054.sba
set break u1054.saa
set break u1054.modsel_out
set break u1054.mpa_out
set break u1054.mpa_en_n
set break u1054.int_en_n
set break u1054.mpb_en_n
set break u1054.mpb_out
set break u1054.sad_en_n
set break u1054.sbd_en_n
set break u1054.modsel_en
set break u1054.sbd_out
set break u1054.sad_out
set break u1054.n_dlen_n
set break u1054.n_dr_out
set break u1054.n_dren_n
set break u1054.n_dl_out


# ******************************************************
#      ctlsvchip
# ******************************************************

set option noblast
set padslimit 2

set stable p54
set stable p55

# sel
set stable p1

# tst
set stable p2

break U9.sv_en
break U9.sv_ld
break U9.prom_dr_n
break U9.ack_dr_n
break U9.ack_out[2]
break U9.ack_out[1]
break U9.ack_out[0]
break U9.sclr_n
break U9.sb_rd_out
break U9.sld
break U9.incadr
break U9.sc[2]
break U9.sc[1]
break U9.sc[0]
break U9.param_dr_n
break U9.partial_xfer
break U9.suspend
break U9.sb_br
break U9.sdr
break U9.ptr_inc
break U9.sbus_err
break U9.pc[1]
break U9.pc[0]
break U9.pcwr
break U9.pldec
break U9.tmint
break U9.eofout
break U9.iosel
break U9.ldctl
break U9.op_shift
break U9.pspty
break U9.ps16
break U9.ps8
break U9.dr
break U9.pdav

break U8.size_dr_n
break U8.sv_on
break U8.sv_sel
break U8.sdh_out[7]
break U8.sdh_out[6]
break U8.sdh_out[5]
break U8.sdh_out[4]
break U8.sdh_out[3]
break U8.sdh_out[2]
break U8.sdh_out[1]
break U8.sdh_out[0]
break U8.sdl_out[7]
break U8.sdl_out[6]
break U8.sdl_out[5]
break U8.sdl_out[4]
break U8.sdl_out[3]
break U8.sdl_out[2]
break U8.sdl_out[1]
break U8.sdl_out[0]
break U8.pd_out[7]
break U8.pd_out[6]
break U8.pd_out[5]
break U8.pd_out[4]
break U8.pd_out[3]
break U8.pd_out[2]
break U8.pd_out[1]
break U8.pd_out[0]
break U8.pdata_dr_n

break u10.u2.u1.u103.u57.zn  u10.u2.u1.u103.u55.a2

### sbus signals ###

# sb_bg_n (input)
set capacitance 100 p4

# sb_clk (input)
set capacitance 100 p13

# sb_pa [3] (input)
set capacitance 100 p47

# sb_pa [2] (input)
set capacitance 100 p14

# sb_d [15]
set capacitance 100 p27

# sb_d [14]
set capacitance 100 p28

# sb_d [13]
set capacitance 100 p29

# sb_d [12]
set capacitance 100 p30

# sb_d [11]
set capacitance 100 p31

# sb_d [10]
set capacitance 100 p32

# sb_d [9]
set capacitance 100 p33

# sb_d [8]
set capacitance 100 p34

# sb_d [7]
set capacitance 100 p35

# sb_d [6]
set capacitance 100 p36

# sb_d [5]
set capacitance 100 p37

# sb_d [4]
set capacitance 100 p38

# sb_d [3]
set capacitance 100 p39

# sb_d [2]
set capacitance 100 p40

# sb_d [1]
set capacitance 100 p41

# sb_d [0]
set capacitance 100 p42


### pbus signals ###

# pb_clk (input)
set capacitance 100 p26


### interchip signals ###

# zin (input)
set capacitance 40 p3

# partial_xfer (input)
set capacitance 40 p5

# eosi (input)
set capacitance 100 p6

# tmint (input)
set capacitance 40 p7

# op_shift (input)
set capacitance 40 p8

# ldctl (input)
set capacitance 40 p9

# sv_en (input)
set capacitance 40 p10

# donep
set capacitance 40 p11

# hnp_sel (i/o)
set capacitance 40 p12

# sbus_err (input)
set capacitance 40 p15

# incadr (input)
set capacitance 40 p16

# sc [2] (input)
set capacitance 40 p17

# sc [1] (input)
set capacitance 40 p18

# sc [0] (input)
set capacitance 40 p19

# sld (input)
set capacitance 40 p20

# decin (input)
set capacitance 40 p21

# suspend (input)
set capacitance 40 p22

# psd_rc
set capacitance 40 p23

# sync_out
set capacitance 100 p24

# sclr_n (input)
set capacitance 40 p25

# cw_flg8
set capacitance 40 p43

# hw_rd
set capacitance 40 p44

# hstop
set capacitance 20 p45

# od_ri
set capacitance 40 p46

# eofin (input)
set capacitance 100 p48

# incout
set capacitance 40 p49

# sv_ld (input)
set capacitance 40 p50

# int_imm
set capacitance 100 p51

# clr_suspend
set capacitance 40 p52

# imm_sync_in (i/o)
set capacitance 40 p53


#***** delay commands ******
### sbus signals ###

# sb_bg_n (input)
show worst p4

# sb_clk (input)
show worst p13

# sb_pa [3] (input)
show worst p47

# sb_pa [2] (input)
show worst p14

# sb_d [15]
show delay start p13 end p27 thru u10.sb_clk

# sb_d [14]
show delay start p13 end p28 thru u10.sb_clk

# sb_d [13]
show delay start p13 end p29 thru u10.sb_clk

# sb_d [12]
show delay start p13 end p30 thru u10.sb_clk

# sb_d [11]
show delay start p13 end p31 thru u10.sb_clk

# sb_d [10]
show delay start p13 end p32 thru u10.sb_clk

# sb_d [9]
show delay start p13 end p33 thru u10.sb_clk

# sb_d [8]
show delay start p13 end p34 thru u10.sb_clk

# sb_d [7]
show delay start p13 end p35 thru u10.sb_clk

# sb_d [6]
show delay start p13 end p36 thru u10.sb_clk

# sb_d [5]
show delay start p13 end p37 thru u10.sb_clk

# sb_d [4]
show delay start p13 end p38 thru u10.sb_clk

# sb_d [3]
show delay start p13 end p39 thru u10.sb_clk

# sb_d [2]
show delay start p13 end p40 thru u10.sb_clk

# sb_d [1]
show delay start p13 end p41 thru u10.sb_clk

# sb_d [0]
show delay start p13 end p42 thru u10.sb_clk


### interchip signals ###

# zin (input)
show worst p3

# partial_xfer (input)
show worst p5

# eosi (input)
show worst p6

# tmint (input)
show worst p7

# op_shift (input)
show worst p8

# ldctl (input)
show worst p9

# sv_en (input)
show worst p10

# donep
show delay start p26 end p11 thru u10.pb_clk

# hnp_sel (i/o)
show delay start p13 end p12 thru u10.sb_clk
show worst p12

# sbus_err (input)
show worst p15

# incadr (input)
show worst p16
show delay start p16 end u10.u2.u1.u103.u1.u27.d

# sc [2] (input)
show worst p17

# sc [1] (input)
show worst p18

# sc [0] (input)
show worst p19

# sld (input)
show worst p20

# decin (input)
show worst p21

# suspend (input)
show worst p22

# psd_rc
show delay start p26 end p23 thru u10.pb_clk

# sync_out
show delay start p26 end p24 thru u10.pb_clk
show delay start p26 end p24 thru U10.U1.U124.U30.u58.i1

# sclr_n (input)
show worst p25

# cw_flg8
show delay start p13 end p43 thru u10.sb_clk

# hw_rd
show delay start p13 end p44 thru u10.sb_clk

# hstop
show delay start p13 end p45 thru u10.sb_clk

# od_ri
# control bit input to opcode reg is
#   not a speed problem
break u10.u2.u2.u64.i1
show delay start p13 end p46 thru u10.sb_clk

# eofin (input)
show worst p48

# incout
show delay start p13 end p49 thru u10.sb_clk
show worst (end) p49

# sv_ld (input)
show worst p50

# int_imm
show delay start p13 end p51 thru u10.sb_clk

# clr_suspend
show delay start p13 end p52 thru u10.sb_clk

# imm_sync_in (i/o)
show delay start p13 end p53 thru u10.sb_clk
show worst p53

# ******************************************************
#      fsmchip
# ******************************************************

set option noblast
set padslimit 2

set stable p54
set stable p55

unbreak u9.*

break U10.donep
break U10.hw_rd
break U10.cw_flg8
break U10.sbdout[15]
break U10.sbdout[14]
break U10.sbdout[13]
break U10.sbdout[12]
break U10.sbdout[11]
break U10.sbdout[10]
break U10.sbdout[9]
break U10.sbdout[8]
break U10.sbdout[7]
break U10.sbdout[6]
break U10.sbdout[5]
break U10.sbdout[4]
break U10.sbdout[3]
break U10.sbdout[2]
break U10.sbdout[1]
break U10.sbdout[0]
break U10.sync_out
break U10.clr_suspend
break U10.od_ri
break U10.incout
break U10.hnp_sel_dr_n
break U10.int_imm_dr_n
break U10.int_imm_out
break U10.psd_rc
break U10.rd_dr_n
break U10.hstop
break U10.hnp_sel_out
break U10.sbd_dr_n


### sbus signals ###

# ack[2]
set capacitance 100 p2

# ack[1]
set capacitance 100 p3

# ack[0]
set capacitance 100 p4

# sb_br
set capacitance 100 p27

# sb_rd
set capacitance 100 p52


# sb_pa[16] (input)
# set capacitance 100 p14

# sb_lerr (input)
# set capacitance 100 p38

# sb_reset_n (input)
# set capacitance 100 p53



### pbus signals ###

# eofin
set capacitance 100 p12

# eofout
set capacitance 100 p23

# iosel
set capacitance 100 p24


### interchip signals ###

# hstop
set capacitance 20 p15

# prom_dr_n
set capacitance 20 p22

# param_dr_n
set capacitance 40 p5

# eosi
set capacitance 40 p6

# sc[2]
set capacitance 40 p31

# sc[1]
set capacitance 40 p32

# sc[0]
set capacitance 40 p33

# pc[1]
set capacitance 40 p45

# pc[0]
set capacitance 40 p46

# tmint
set capacitance 30 p47

# sv_ld
set capacitance 40 p48


# incadr
set capacitance 40 p34

# sld
set capacitance 40 p30

# sbus_err
set capacitance 100 p35

# ps16
set capacitance 40 p42

# pspty
set capacitance 40 p41

# pcwr
set capacitance 10 p40

# pldec
set capacitance 40 p39

# ldctl
set capacitance 40 p37

# sv_en
set capacitance 40 p36

# sv_on
set capacitance 40 p7

# op_shift
set capacitance 40 p8

# ptr_inc
set capacitance 40 p9

# sv_sel
set capacitance 40 p10

# sdr
set capacitance 40 p11

# cw
set capacitance 40 p29

# flg8
set capacitance 80 p28

# sclr_n
set capacitance 80 p50

# partial_xfer
set capacitance 40 p51


### inputs ###

# rd
# set capacitance 10 p49


### display delays ###

# ack[2]
show delay start p13 end p2 thru u9.sb_clk_n

# ack[1]
show delay start p13 end p3 thru u9.sb_clk_n

# ack[0]
show delay start p13 end p4 thru u9.sb_clk_n

# sb_br
show delay start p13 end p27 thru u9.sb_clk_n

# sb_rd
show delay start p13 end p52 thru u9.sb_clk_n

# sb_pa[16] (input)
show worst p14

# sb_lerr (input)
show worst p38

# sb_reset_n (input)
show worst p53


### pbus signals ###

# eofin (input)
show worst p12

# eofout
show delay start p26 end p23 thru u9.pb_clk_n

# iosel
show delay start p26 end p24 thru u9.pb_clk_n


# prom_dr_n
show delay start p13 end p22 thru u9.sb_clk_n

# param_dr_n
show delay start p13 end p5 thru u9.sb_clk_n

# eosi (input)
show worst p6

# sc[2]
show delay start p13 end p31 thru u9.sb_clk_n

# sc[1]
show delay start p13 end p32 thru u9.sb_clk_n

# sc[0]
show delay start p13 end p33 thru u9.sb_clk_n

# pc[1]
show delay start p26 end p45 thru u9.pb_clk_n

# pc[0]
show delay start p26 end p46 thru u9.pb_clk_n

# tmint
show delay start p13 end p47 thru u9.sb_clk_n

# sv_ld
show delay start p13 end p48 thru u9.sb_clk_n


# incadr
show delay start p13 end p34 thru u9.sb_clk_n

# sld
show delay start p13 end p30 thru u9.sb_clk_n

# sbus_err
show delay start p13 end p35 thru u9.sb_clk_n

# ps16
show delay start p26 end p42 thru u9.pb_clk_n

# pspty
show delay start p26 end p41 thru u9.pb_clk_n

# pcwr
show delay start p26 end p40 thru u9.pb_clk_n

# pldec
show delay start p26 end p39 thru u9.pb_clk_n

# ldctl
show delay start p26 end p37 thru u9.pb_clk_n

# sv_en
show delay start p13 end p36 thru u9.sb_clk_n

# sv_on
show delay start p13 end p7 thru u9.sb_clk_n

# op_shift
show delay start p26 end p8 thru u9.pb_clk_n

# ptr_inc
show delay start p26 end p9 thru u9.pb_clk_n

# sv_sel
show delay start p13 end p10 thru u9.sb_clk_n

# sdr
show delay start p13 end p11 thru u9.sb_clk_n

# cw
show delay start p26 end p29 thru u9.pb_clk_n

# flg8
show delay start p26 end p28 thru u9.pb_clk_n

# sclr_n
show delay start p13 end p50 thru u9.sb_clk_n

# partial_xfer
show delay start p13 end p51 thru u9.sb_clk_n


### inputs ###

# hstop
show worst p15

# rd
show worst p49


# ******************************************************
#      dataregs
# ******************************************************

set option noblast
set padslimit 2

set stable p54
set stable p55

unbreak u8.*
break U9.*


### sbus signals ###

# sb_sz [0] (i/o)
set capacitance 100 p4

# sb_bg_n
set capacitance 100 p24

# sb_as
set capacitance 100 p52

# sb_sel (input)
set capacitance 100 p51

# sb_clk (input)
set capacitance 100 p13

# sdh [7]
set capacitance 100 p27

# sdh [6]
set capacitance 100 p28

# sdh [5]
set capacitance 100 p29

# sdh [4]
set capacitance 100 p30

# sdh [3]
set capacitance 100 p31

# sdh [2]
set capacitance 100 p32

# sdh [1]
set capacitance 100 p33

# sdh [0]
set capacitance 100 p34

# sdl [7]
set capacitance 100 p35

# sdl [6]
set capacitance 100 p36

# sdl [5]
set capacitance 100 p37

# sdl [4]
set capacitance 100 p38

# sdl [3]
set capacitance 100 p39

# sdl [2]
set capacitance 100 p40

# sdl [1]
set capacitance 100 p41

# sdl [0]
set capacitance 100 p42


### pbus signals ###

# pb_clk (input)
set capacitance 100 p26

# pd [7] (i/o)
set capacitance 100 p5

# eofin (input)
set capacitance 100 p48

# eofout (input)
set capacitance 100 p50

# pd [6] (i/o)
set capacitance 100 p6

# pd [5] (i/o)
set capacitance 100 p7

# pd [4] (i/o)
set capacitance 100 p8

# pd [3] (i/o)
set capacitance 100 p9

# pd [2] (i/o)
set capacitance 100 p10

# pd [1] (i/o)
set capacitance 100 p11

# pd [0] (i/o)
set capacitance 100 p12


### interchip signals ###

# pc [0] (input)
set capacitance 100 p47

# sdr (input)
set capacitance 100 p14

# sb_sz [1] (i/o)
set capacitance 40 p3

# sld (input)
set capacitance 40 p15

# sc [2] (input)
set capacitance 40 p16

# sc [1] (input)
set capacitance 40 p17

# sc [0] (input)
set capacitance 40 p18

# dr (input)
set capacitance 40 p19

# immed (input)
set capacitance 40 p20

# ps8 (input)
set capacitance 40 p21

# ps16 (input)
set capacitance 40 p22

# pspty (input)
set capacitance 40 p23

# sclr_n (input)
set capacitance 40 p25

# op_data (input)
set capacitance 40 p43

# flg8 (input)
set capacitance 40 p44

# op_shift (input)
set capacitance 40 p45

# pc [1] (input)
set capacitance 40 p46

# sv_sel
set capacitance 40 p49

# ptr_inc (input)
set capacitance 40 p53


#***** delay commands ******


### sbus signals ###

# sb_sz [0] (i/o)
show worst p4
show delay start p13 end p4 thru u8.sb_clk_n

# sb_bg_n (input)
show worst p24

# sb_as (input)
show worst p52

# sb_sel (input)
show worst p51

# sb_clk (input)
show worst p13

# sdh [7] (i/o)
show worst p27
show delay start p13 end p27 thru u9.sb_clk_n

# sdh [6] (i/o)
show worst p28
show delay start p13 end p28 thru u9.sb_clk_n

# sdh [5] (i/o)
show worst p29
show delay start p13 end p29 thru u9.sb_clk_n

# sdh [4] (i/o)
show worst p30
show delay start p13 end p30 thru u9.sb_clk_n

# sdh [3] (i/o)
show worst p31
show delay start p13 end p31 thru u9.sb_clk_n

# sdh [2] (i/o)
show worst p32
show delay start p13 end p32 thru u9.sb_clk_n

# sdh [1] (i/o)
show worst p33
show delay start p13 end p33 thru u9.sb_clk_n

# sdh [0] (i/o)
show worst p34
show delay start p13 end p34 thru u9.sb_clk_n

# sdl [7] (i/o)
show worst p35
show delay start p13 end p35 thru u9.sb_clk_n

# sdl [6] (i/o)
show worst p36
show delay start p13 end p36 thru u9.sb_clk_n

# sdl [5] (i/o)
show worst p37
show delay start p13 end p37 thru u9.sb_clk_n

# sdl [4] (i/o)
show worst p38
show delay start p13 end p38 thru u9.sb_clk_n

# sdl [3] (i/o)
show worst p39
show delay start p13 end p39 thru u9.sb_clk_n

# sdl [2] (i/o)
show worst p40
show delay start p13 end p40 thru u9.sb_clk_n

# sdl [1] (i/o)
show worst p41
show delay start p13 end p41 thru u9.sb_clk_n

# sdl [0] (i/o)
show worst p42
show delay start p13 end p42 thru u9.sb_clk_n


### pbus signals ###

# pb_clk (input)
show worst p26

# eofin (input)
show worst p48

# eofout (input)
show worst p50

# pd [7] (i/o)
show worst p5
show delay start p26 end p5 thru u9.pb_clk

# pd [6] (i/o)
show worst p6
show delay start p26 end p6 thru u9.pb_clk

# pd [5] (i/o)
show worst p7
show delay start p26 end p7 thru u9.pb_clk

# pd [4] (i/o)
show worst p8
show delay start p26 end p8 thru u9.pb_clk

# pd [3] (i/o)
show worst p9
show delay start p26 end p9 thru u9.pb_clk

# pd [2] (i/o)
show worst p10
show delay start p26 end p10 thru u9.pb_clk

# pd [1] (i/o)
show worst p11
show delay start p26 end p11 thru u9.pb_clk

# pd [0] (i/o)
show worst p12
show delay start p26 end p12 thru u9.pb_clk


### interchip signals ###

# pc [0] (input)
show worst p47

# sdr (input)
show worst p14

# sb_sz [1] (i/o)
show worst p3
show delay start p13 end p3 thru u9.sb_clk_n

# sld (input)
show worst p15

# sc [2] (input)
show worst p16

# sc [1] (input)
show worst p17

# sc [0] (input)
show worst p18

# dr (input)
show worst p19

# immed (input)
show worst p20

# ps8 (input)
show worst p21

# ps16 (input)
show worst p22

# pspty (input)
show worst p23

# sclr_n (input)
show worst p25

# op_data (input)
show worst p43

# flg8 (input)
show worst p44

# op_shift (input)
show worst p45

# pc [1] (input)
show worst p46

# sv_sel
show delay start p13 end p49 thru u9.sb_clk_n

# ptr_inc (input)
show worst p53