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\chapter{The \CHIP}

As explained in the \HR, each module contains sixteen copies of the \chip---a
custom \vlsi\ chip that one may view as embodying the \step\
architecture.\footnote
	{In the present version of the \step\ system, the \chip\ is but one
of the four personalities of a die called the \die.  The other three
personalities of this die are chips used by the \step\ controller (documented
in \CT). A specific die personality is selected by hardwiring two chip-select
lines.

The \die\ is realized on a 1.2-micron gate array (made by VLSI Technology)
with two levels of metallization. The \chip\ personality uses approximately
16K gates; the other three personalities, a total of about 9K gates.}

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Thus, for example, module \id|dataregs| is documented by the
schematics \id|dataregs.ps|, while module \id|pty_p| is documented
by the state machine \id|pty.sm|.


The schematics document different levels of the design hierarchy. 
The nodes of the hierarchy tree are called \tdf{modules}.\footnote
	{These are Valid design modules, not to be confused with the physical
modules that make up a \step\ system.}
	The top of the hierarchy tree for the entire die has the following
structure
 \begin{verbatim}
    chip
        cam
        ctlsvchip
        dataregs
        fsmchip\end{verbatim}
 \noindent where \id|cam| is the \chip, while \id|ctlsvchip|, \id|dataregs|,
and \id|fsmchipand| are the three controller chips.
