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\section{Serial input}

The serial address starts with the value that was loaded by CAS*
during the previous Write Transfer operation.  At the rising edge of
SC, if SE* is low the current serial data are written to the current
serial address (input data must be held for $t_{SDH}$); then,
independently of SE*, the serial address is incremented.

\section{Serial output}

The serial address starts with the value that was loaded by CAS*
during the previous Read Transfer operation. At the rising edge of SC,
the value at this address will be placed on the output latch, and will
appear on the SDQ line (after no longer than $t_{SAC}$; the previous
data will have been held for no less than $t_{SCH}$) if SE* is low;
then, independently of SE*, the serial address is incremented.


\section{Transfer and refresh cycles}

HTAB* is used as a clock enable for the vertical counter; thus, any incrementing
of the vertical counter takes place only at the rising edge of HTAB*, and this
counter remains constant between HTAB*s. The time between two consecutive
rising edges of HTAB* is called a {\em line}.


On each line on which VRUN is valid the following operations are
performed
 \begin{itemize}
	\item Right at the beginning of the line, before HRUN starts,
a Read Transfer operation is performed only is the frame
buffer is in hold mode. 
	\item As soon as HRUN is over, a
Write Transfer operation is performed.\footnote
	{If we are in hold mode, we just write back to DRAM the row that
we last read; the vertical count hasn't changed yet.}
	\item This is immediately followed by two consecutive CAS-before-RAS cycles.
 \end{itemize}



















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