% -*- Mode:Text -*- 

\chapter{\STEP\ module}\label{sect.module}

Physically, a \cam\ module consists of a printed circuit board which
plugs into a slot of a \cam\ box motherboard (see \sect{box-overview})
by means of a row of high-density edge connectors. The overall
interconnection pattern for a box consisting of a motherboard and up
to eight modules is sketched in \fig{backplane} from the viewpoint
of the motherboard, and in \fig{mod-pins} from the viewpoint of a module.

The fundamental function of a module is to implement the data-stream loop of
\fig{module-loop}: the layer \dram{}s are sequentially scanned, and their
contents streamed through a \sram\ lookup table. Scan parameters and detailed
data routing are controlled by the \chip{}s through the scanning/gluing
circuitry of \fig{scanning}.

\figonecol{module-loop}{\psfig{file=fig/module-loop.ps}}{Basic form of a
module's data-stream loop: the \dram{}s are orderly scanned and their
contents streamed through an \sram\ lookup table.}


\section{Module pin types}\label{sect.mod-pin-types}

\input mod-pin-types

The pins are sorted into functional groups, each of which is discussed
in a separate section. In the pinout table in each section, the table
header gives the total number of pins in the group and a descriptive
name for the group itself (\bus\ interface, glue, video, etc.). For
each pin, the tables give the pin type, according to table
\eq{m-pin-types}, and the pin's mnemonics followed by its full name.

Module pin names are distinguished by the prefix `{\sym M/}',
to avoid confusion with \chip\ or box pin names.

\medskip

As mentioned in \sect{interbox}, communication between \cam\ boxes (as
well as between the controller and the corner box) takes place on
transmission lines. The present pinout specifications are compatible
with either unbalanced (e.g., coax cable) or balanced (e.g., twisted
pair) transmission lines. In either case there are a {\em pair} of
pins associated with each signal. Depending on the implementation, the
two elements of the pair would be called ``tip'' and ``ring,''
``core'' and ``shield,'' ``signal'' and ``return,'' ``plus'' and
``minus,'' or similar names.  Here we'll use the noncommittal
designators `A' and `B'.

In the pinout tables below, a signal-type designator ending with the
character `2' (cf.\ table \eq{m-pin-types}) denotes a transmission
line pair, listed as a single entry but with the understanding that
two pins are involved.  Thus, an entry of the form
 $$
 \begin{tabular}{|l|ll|}\hline
	\pin{\OutP}{M/FB*}{M/Frame Branch*}\hline
 \end{tabular}
 $$

\noindent implies the existence of two pins, namely
{\sym M/Frame Branch A*} and {\sym M/Frame Branch B*}.

Some of the transmission lines terminate on the motherboard ({\sym
\bus\ root} lines in \fig{mod-pins}), where they are handled by
discrete drivers and receivers appropriate to the type of line.  Most
of the transmission lines, however, terminate directly on the module
boards (e.g., {\sym XM glue} or {\sym \bus\ branch} in \fig{mod-pins})
and are associated with individual \chip\ pins. If these pins have
sufficiently powerful internal drivers, they will be able to drive
unbalanced transmission lines directly, i.e., without the need for
separate discrete drivers.  In what follows, we shall assume that this
is the case; however, the module pinout will not change if discrete
drivers are inserted between the \chip\ pins and the transmission
lines, and/or if balanced transmission lines are used.

Note that the pins of motherboard connectors {\sym XM glue} through
{\sym ZP glue} and {\em Tbus branch} (cf.\ \fig{mod-pins}) are not
connected to any signal traces on the motherboard;\footnote
	{In the case of unbalanced transmission lines, the B side
of each pair would probably be tied to the ground plane.}
	they simply provide mechanical support and passive feedthrough
from the modules to the transmission lines.

 
 \begin{equation}\label{eq.m-pin-types}
 \begin{tabular}{|@{\,}c@{\,}|p{2.3in}|}\hline 
type & \multicolumn{1}{c|}{description} \\\hline\hline
 \In & \parhead{Input} Input signal driving a
discrete on-board buffer which fans out the signal to the sixteen
\chip{}s of the module.\\\hline
 \Out & \parhead{Output} Output signal driven by the {\sym Low-Drive
Multipurpose Pin} of one of the sixteen \chip{}s.\\\hline
 \IO & \parhead{Bidirectional} This pin is sensed as an input, and is
driven as a tri-state output.\\\hline
 \InP & \parhead{Input pair} Pair of pins (A and B) at the receiving
end of a transmission line.\\\hline
 \OutP & \parhead{Output pair} Pair of pins (A and B) driving a
transmission line.\\\hline
 \IOP & \parhead{Bidirectional pair} Pair of pins (A and B)
which may drive or sense a transmission line.\\\hline
 \end{tabular}
 \end{equation}

\section{\bus\ interface}\label{sect.m-tbus-pins}

 \begin{pinout}{module-bus-local}{...}{\sym \bus\ local}
	\pin{\IO}{Local.D[0:F]}{Local Data[0:F]}
	\pin{\In}{Local.Reset*}{Local Reset*}
	\pin{\In}{Local.Sync*}{Local Sync*}
	\pin{\In}{Local.Frame*}{Local Frame*}
	\pin{\In}{Local.OH}{Local Outbound Handshake}
	\pin{\Out}{Local.IH}{Local Inbound Handshake}
	\pin{\Out}{Local.Status*}{Local Status*}
 \end{pinout}

 \begin{pinout}{module-bus-branch}{...}{\sym \bus\ branch}
	\pin{\IOP}{Branch.D[0:F]}{Branch Data[0:F]}
	\pin{\OutP}{Branch.Reset*}{Branch Reset*}
	\pin{\OutP}{Branch.Sync*}{Branch Sync*}
	\pin{\OutP}{Branch.Frame*}{Branch Frame*}
	\pin{\OutP}{Branch.OH}{Branch Outbound Handshake}
	\pin{\InP}{Branch.IH}{Branch Inbound Handshake}
	\pin{\InP}{Branch.Status*}{Branch Status*}
 \end{pinout}

The {\sym \bus\ local} signals are handled by the motherboard,
which fans out to the eight modules signals coming
from the host ({\sym \bus\ root} connector), and {\sc or}s signals
from eight modules into a single hostward signal.

The {\sym \bus\ branch} signals represent the place where a subtree of the
\bus\ tree can be grafted.

\section{Glue}\label{sect.m-glue-pins}

 \begin{pinout}{module-glue}{192}{\sym Glue}
	\pin{\IO2}{Glue0.G[0:F]}{Glue X-Minus[0:F]}
	\pin{\IO2}{Glue1.G[0:F]}{Glue X-Plus[0:F]}
	\pin{\IO2}{Glue2.G[0:F]}{Glue Y-Minus[0:F]}
	\pin{\IO2}{Glue3.G[0:F]}{Glue Y-Plus[0:F]}
	\pin{\IO2}{Glue4.G[0:F]}{Glue Z-Minus[0:F]}
	\pin{\IO2}{Glue5.G[0:F]}{Glue Z-Plus[0:F]}
 \end{pinout}

These are the signals that allow one to glue modules edge-to-edge so
as to achieve an array of indefinite extent.  Each glue signal runs
point-to-point (no fan-out or fan-in) between two modules; in a large
system, the two modules will reside in different boxes.


\section{Data stream}\label{sect.m-stream-pins}

 \begin{pinout}{module-flywheel}{...}{\sym Data flywheel}
	\pin{Out}{Flywheel.O[0:F]}{Flywheel Data Output[0:F]}
	\pin{In}{Flywheel.I[0:F]}{Flywheel Data Input[0:F]}
	\pin{Out}{Flywheel.Clock}{Flywheel Clock} 
	\pin{Out}{Flywheel.DSV*}{Flywheel Data Stream Valid*} 
 \end{pinout}

 \begin{pinout}{module-video}{...}{\sym Raw video}
	\pin{IO}{Local.Video[0:F]}{Local Video[0:F]}
 \end{pinout}

\section{Wired-AND communication}\label{sect.wired-and}

