 % -*- Mode:TeX -*- 
\documentstyle{article}
\input cam8form.tex

\begin{document}
\input notecomm.tex
\input notemath.tex

\let\sym\sf	    % symbols done in sans serif
%\let\sym\tt	    % symbols done in \tt
\newcommand{\symdex}[1]{{\sym #1}}

\newcommand{\cam}{{\sc cam}}
\newcommand{\Cam}{{\sc Cam}}
\newcommand{\dram}{{\sc dram}}
\newcommand{\Dram}{{\sc Dram}}
\newcommand{\sram}{{\sc sram}}
\newcommand{\Sram}{{\sc Sram}}

\title{Heart chip pinout}

\maketitle
    \begin{history}
	\item TT, 14 Dec 1989\quad started
    \end{history}	

\newcommand{\In}{{\tt I}}	% input only
\newcommand{\Out}{{\tt O}}	% output, always driven
\newcommand{\TS}{{\tt T}}	% output, can be disabled
\newcommand{\IO}{{\tt B}}	% bidirectional (In+TS}
\newcommand{\Wor}{{\tt W}}	% wire-OR
\newcommand{\Vdd}{{\tt P}}	% power
\newcommand{\Gnd}{{\tt G}}	% ground
\newcommand{\mnemo}[1]{{\sl #1}.\quad}
\newcommand{\sline}[2]{\symdex{#1}\hfill#2}


\section{Pinout}

Here we document the (tentative) pinout of \cam-8's heart chip.

The pins are sorted into functional groups (\dram\ interface,
Tbus interface, etc.).

In the following pinout tables, each pin name is followed by
a one-character code specifying the pin type as follows
 \begin{table}[h]
 $$
 \begin{tabular}{|c|p{2.25in}|}\hline 
 Type & \multicolumn{1}{c|}{Description} \\\hline\hline
 \In & \mnemo{Input} This pin is sensed as an input.\\\hline
 \Out & \mnemo{Output} This pin has an output driver, which is always
enabled.\\\hline
 \TS & \mnemo{Tri-state} This pin has an output driver which can
be disabled.\\\hline
 \IO & \mnemo{Bidirectional} This pin is sensed as an input, and is
driven as a tri-state output.\\\hline
 \Wor & \mnemo{Wire-{\sc or}} This pin is driven in a way suitable for
wire-{\sc or}ing (implementation details to be decided).\\\hline
 \end{tabular}
 $$
 \caption{Pin types.}\label{pin types}
 \end{table}

\subsection{DRAM interface}

 \begin{table}[h]
 $$
 \begin{tabular}{|c|p{2.25in}|}\hline 
 Name\hfill\ Type & \multicolumn{1}{c|}{Description} \\\hline\hline
 \sline{DA\rm[0:10]}{\Out} & \mnemo{\dram\ address} Directly drives
\dram\ multiplexed row/column address lines.\footnotemark\\\hline
 \sline{DD\rm[0:3]}{\IO} & \mnemo{\dram\ data} Directly drives or
senses \dram\ data lines.\footnotemark\\\hline
 \sline{DRAS*}{\Out} & \mnemo{\dram\ row address strobe} Directly
drives \dram\ $\overline{\rm RAS}$ line.\\\hline
 \sline{DCAS*}{\Out} & \mnemo{\dram\ column address strobe} Directly
drives \dram\ $\overline{\rm CAS}$ line.\\\hline
 \sline{DWT*}{\Out} & \mnemo{\dram\ write enable} Directly drives \dram\
$\overline{\rm W}$ line.\\\hline
 \sline{DOE*}{\Out} & \mnemo{\dram\ write enable} Directly drives
\dram\ $\overline{\rm G}$ line.\\\hline
 \end{tabular}
 $$
 \caption{\Dram\ interface: 19 lines (11 address, 4 data, 4
control.}\label{tab.dram interface pins}
 \end{table}

\addtocounter{footnote}{-1}\footnotetext
	{Since we use nybble-wide chips, total \dram\ capacity with 11
address lines is $2^{2\cdot 11}\cdot 4$, or 16M bits.}
\addtocounter{footnote}{1}\footnotetext
	{Once we are in fast-page or static-column mode, typically a
\dram\ read/write operation takes 4 clock cycles; in the first two, a
nybble is read, in the second, a nybble is written.}

\subsection{SRAM interface}

 \begin{table}[h]
 $$
 \begin{tabular}{|c|p{2.25in}|}\hline 
 Name\hfill\ Type & \multicolumn{1}{c|}{Description} \\\hline\hline
 \sline{SAA}{\Out} & \mnemo{\sram-A address} \\\hline
 \sline{SBA}{\Out} & \mnemo{\sram-B address} \\\hline
 \sline{SAD}{\IO} & \mnemo{\sram-A data} \\\hline
 \sline{SBD}{\IO} & \mnemo{\sram-B data} \\\hline
 \sline{SMC}{\Out} & \mnemo{\sram\ multipurpose control} \\\hline
 \end{tabular}
 $$
 \caption{\Sram\ interface.}\label{tab.sram interface pins}
 \end{table}

\subsection{Glue}

 \begin{table}[h]
 $$
 \begin{tabular}{|c|p{2.25in}|}\hline 
 Name\hfill\ Type & \multicolumn{1}{c|}{Description} \\\hline\hline
 \sline{XP}{\IO} & \mnemo{$x_+$ glue} \\\hline
 \sline{XM}{\IO} & \mnemo{$x_-$ glue} \\\hline
 \sline{YP}{\IO} & \mnemo{$y_+$ glue} \\\hline
 \sline{YM}{\IO} & \mnemo{$y_-$ glue} \\\hline
 \sline{ZP}{\IO} & \mnemo{$z_+$ glue} \\\hline
 \sline{ZM}{\IO} & \mnemo{$z_-$ glue} \\\hline
 \sline{EC}{?} & \mnemo{Error compare} \\\hline
 \end{tabular}
 $$
 \caption{Glue.}\label{tab.glue interface pins}
 \end{table}

\subsection{Flywheel bus}

 \begin{table}[h]
 $$
 \begin{tabular}{|c|p{2.25in}|}\hline 
 Name\hfill\ Type & \multicolumn{1}{c|}{Description} \\\hline\hline
 \end{tabular}
 $$
 \caption{Flywheel bus.}\label{tab.flywheel pins}
 \end{table}

\subsection{Tbus interface}

 \begin{table}[h]
 $$
 \begin{tabular}{|c|p{2.25in}|}\hline 
 Name\hfill\ Type & \multicolumn{1}{c|}{Description} \\\hline\hline
 \sline{TD}{\IO} & \mnemo{Tbus data} \\\hline
 \sline{TW*}{\In} & \mnemo{Tbus write enable} \\\hline
 \sline{TE*}{\IO} & \mnemo{Tbus enable} \\\hline
 \sline{TD*}{\In} & \mnemo{Tbus downstream enable} \\\hline
 \sline{TU*}{\Out} & \mnemo{Tbus upstream enable} \\\hline
 \sline{Clock2*}{\In} & \mnemo{Tbus 2\by clock} \\\hline
 \sline{Tab*}{\Wor} & \mnemo{Tbus tab} \\\hline
 \sline{ModSel}{\Wor} & \mnemo{Module select} \\\hline
   \end{tabular}
 $$
 \caption{Tbus interface.}\label{tab.Tbus interface pins}
 \end{table}


\end{document}

 \sline{VDD}{\Vdd} & \mnemo{Power} \\\hline
 \sline{GND}{\Gnd} & \mnemo{Ground} \\\hline
