% -*- Mode:Text -*- 

\chapter{\chip}\label{sect.chip}

\fig{chip-top} shows in a very schematic way the logical
organization of a \chip, especially in relation to the chip's
immediate surroundings.

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	\put(76,172){\makebox(0,0){\footnotesize\shortstack{data\\flywheel}}}
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	\put(112,160){\framebox(64,16){\sc sram}}
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	\put(152,48){\shortstack[l]{other\\{\sc step}\\chips\\in the\\same\\module}}
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 {Logical organization of a \chip\ and its immediate surroundings. See
text for details.}

Some of the \chip's \io\ lines (\sect{pinout}) connect it to other
circuitry on the same module, some to homologous \chip{}s on adjacent
modules, some to the \bus, and some to optional external circuitry.
These different types of interconnection are better understood with
reference to the \chip's functions, as detailed below.

\medskip

Though physically residing on a separate memory chip, the block labeled
\dram\ should logically be treated as part of the \chip, since all of its
inputs and outputs are directly handled by the latter.

The main function of the \chip\ is to pump a data stream out of and
then back into the \dram. Along its course, the data stream may be modified
by
 \begin{itemize}
	\item Data exchanges with adjacent modules, via the {\em glue lines}, to
achieve indefinite spatial extension for the array of sites.
	\item Real-time data exchanges with optional external
circuitry, via the {\em data flywheel} (\sect{}).
	\item Real-time output to a raster-scan monitor, via the {\em
raw video bus} (\sect{}). All modules tristate their video lines onto
a single {\sym Raw video} bus, so that video output from any single
module can be routed to the monitor.
	\item Data replacement by lookup in the \sram\ table. The
table is shared by the 16 \chip{}s of a module, each of which provides
one bit of the lookup {\em key} (table address) and and receives one
bit of the corresponding {\em entry} (table data). Of course, this
collective lookup is the main mechanism for interaction between data
streams, and ultimately for the realization of the desired dynamical
behavior as well as of real-time analysis.
 \end{itemize}

The \bus\ (\chapt{bus}) is the exclusive channel of communication between
the host and the \cam\ modules. All exchanges between the host and
\sram\ or \dram\ chips are mediated by the \chip.

Beside being mutually coupled via the \sram\ table, the 16 \chip{}s of
a module are also mutually coupled via a wire-{\sc and} {\sym ModSel}
line for the purpose of responding as a single addressable entity to
\bus\ operations (\sect{modselect}), and a wire-{\sc and} {\sym Int*}
line for collecting interrupts from the sixteen chips and eventually
merging them onto the \bus\ {\sym Status} line.


\section{\chip\ block diagram}

The internal structure of the \chip\ shown in \fig{chip-top} is
further detailed in \fig{chip-capt}, which is taken from the \chip's
actual design files (this diagram does not show the \io\ buffers
that interface the internal signals to the outside world).

%\figtwogiven{chip-capt}{\psfig{figure=fig/chip-capt.ps,height=8.4in}}
\figtwogiven{chip-capt}{\psfig{figure=fig/chip-capt-dum.ps,height=8.4in}}{\chip\
block diagram, taken from actual design files.}


\section{Pinout}\label{chip-pinout}

\subsection{Chip pin types}

The \cam\ chip is packaged in a 68-pin PLCC.

The pins are sorted into functional groups, each of which is discussed
in a separate section. In the pinout table in each subsection, the
table header gives the total number of pins in the group and a
descriptive name for the group itself (\dram\ interface, \bus\
interface, etc.). For each pin, the tables give the pin number, its
type, according to table \eq{pin-types}, and then the pin's
mnemonics followed by its full name.

 \def\In{{\tt I}}
 \def\Out{{\tt O}}
 \def\TS{{\tt T}}
 \def\IO{{\tt B}}
 \def\Wand{{\tt W}}
  
 \begin{equation}\label{eq.pin-types}
 \begin{tabular}{|c|p{2.0in}|}\hline 
 type & \multicolumn{1}{c|}{description} \\\hline\hline
 \In & \parhead{Input} This pin is sensed as an input.\\\hline
 \Out & \parhead{Output} This pin has an output driver, which is always
enabled.\\\hline
 \TS & \parhead{Tri-state} This pin has an output driver which can
be disabled.\\\hline
 \IO & \parhead{Bidirectional} This pin is sensed as an input, and is
driven as a tri-state output.\\\hline
 \Wand & \parhead{Wire-{\sc and}} This pin is driven in a way suitable for
wire-{\sc and}ing.\\\hline
 \end{tabular}
 \end{equation}



\subsection{DRAM interface}\label{sect.dram-side-pins}

 \begin{pinout}{chip-dram}{19}{\Dram\ interface}
 \pin{\Out}{DA(10:0)}{DRAM Address(10:0)}
 \pin{\IO}{DD(3:0)}{DRAM Data(3:0)}
 \pin{\Out}{DRAS*}{DRAM Row Address Strobe*}
 \pin{\Out}{DCAS*}{DRAM Column Address Strobe*}
 \pin{\Out}{DWE*}{DRAM Write Enable*}
 \pin{\Out}{DOE*}{DRAM Output Enable*}
 \end{pinout}

These are the address, data, and control signals for the \dram\ chip
associated with each \chip. 

\medskip

Since we use nybble-wide chips, total \dram\ capacity with 11 address
lines ({\sym DA(10:0)}) is $4\cdot2^{2\cdot 11}$, or 16 Mbits.

Once we are in fast-page or static-column mode, typically a \dram\
read/write operation takes 4 clock cycles; in the first two, a nybble
is read, in the second, a nybble is written.

\subsection{SRAM interface}\label{sect.sram-side-pins}

 \begin{pinout}{chip-sram}{4}{\Sram\ interface}
 \pin{\Out}{SA0}{SRAM Address, Bank 0}
 \pin{\Out}{SA1}{SRAM Address, Bank 1}
 \pin{\IO}{SD0}{SRAM Data, Bank 0}
 \pin{\IO}{SD1}{SRAM Data, Bank 1}
 \end{pinout}

These are the address and data signals for the two \sram\ lookup
tables, \lut0 and \lut1.  The \sram\ control signals are distributed
on a module-wide basis by means of four of the {\sym Multipurpose}
pins (\sect{MPCR}).

\subsection{Glue}\label{sect.glue-pins}

 \begin{pinout}{chip-glue}{6}{Glue}
 \pin{\IO}{XM}{X-Minus}
 \pin{\IO}{XP}{X-Plus}
 \pin{\IO}{YM}{Y-Minus}
 \pin{\IO}{YP}{Y-Plus}
 \pin{\IO}{ZM}{Z-Minus}
 \pin{\IO}{ZP}{Z-Plus}
 \end{pinout}

These are the signals that allow one to ``glue'' modules edge-to-edge
so as to achieve an array of indefinite extent.

\subsection{Data stream}\label{sect.flywheel-pins}

 \begin{pinout}{chip-flywheel}{3}{Data stream}
	\pin{\Out}{FDO}{Flywheel Data Output}
	\pin{\In}{FDI}{Flywheel Data Input}
	\pin{\TS}{Video}{Video}
 \end{pinout}

At every step, the entire \dram\ contents (or whatever fraction of it
is actually used for the model's state variables) is serially made
visible to the outside world via the {\sym Flywheel Data Output} pin,
before being sent to the lookup table.  External circuitry can use
these data for analysis purposes; and can replace any of
these data bits with externally supplied ones. On every
clock cycle in which {\sym 
Enable*} is asserted, the internal data bit is replaced
with one that is externally supplied via the {\sym Flywheel Data Input}
pin. The timing of this injection---either one or four clock cycles\footnote
	{Depending on the setting of the {\sym FPL} bit in the
{\sym Hardware Environment Register} (\sect{HER}).}
	later than when the original bit appeared on the {\sym FDO}
pin---allows for the original bit to be taken into consideration
when generating the replacement bit.

\subsection{\bus\ interface}\label{sect.tbus-interface}

 \begin{pinout}{chip-bus}{5}{\bus}
	\pin{\In}{TF*}{\bus\ Frame*}
	\pin{\In}{TOT}{\bus\ Outbound Tag}
	\pin{\In}{TIT}{\bus\ Inbound Tag}
	\pin{\IO}{TD}{\bus\ Data}
	\pin{\IO}{TDB}{\bus\ Data Branch}
	\pin{\In}{Sync*}{Sync*}
	\pin{\In}{Reset*}{Reset*}
 \end{pinout}

The following output signals are produced on a per-module rather than
per-chip bases, and are handled by a multipurpose pin:
 {\sym \bus\ Inbound Tag Local} ({\sym TITL}),
 {\sym \bus\ Outbound Tag Branch} ({\sym TOTB}),
 {\sym \bus\ Frame Branch*} ({\sym TFB*}),
 {\sym \bus\ Sync Branch*} ({\sym TSB*}),


Other \bus\ related signals go through significant on-board conditioning,
and are listed in \sect{misc-pins}.

\subsection{Miscellaneous}\label{sect.misc-pins}

 \begin{pinout}{chip-misc}{9}{Miscellaneous}
 \pin{\In}{Clock}{Clock}
 \pin{\Out}{MP}{Multipurpose}
 \pin{\Wand}{Int*}{Interrupt*}
 \pin{\Wand}{ModSel}{Module Select}
 \end{pinout}


The {\sym Interrupt*} pins from the 16 chips of a module are wire-{\sc
or}ed together. The resulting signal is merged with {\sym
Scan-in-Progress} information and output on one of the 16 {\sym
Multipurpose} pins (\sect{MPCR}), to be used, after proper
conditioning, as the \bus\ {\sym Status*} signal contributed by the module.

The {\sym Module Select} pins from the 16 chips of a module are
wire-{\sc and}ed together, to allow the individual chips to contribute
to a module-wide {\sc and} and sense its result, as explained in
\sect{modselect}. As each pin will be actively driven immediately
before the clock cycle in which the {\sc and} operation will be
performed, the pull-up resistor connected to this wire is only for
long-term bleeding purposes,

{\sym Reset*} and {\sym Clock} are derived from the corresponding
\bus\ signals. Redistribution of these signals to the tree branches
is handled by on-board discrete circuitry rahter than by the \chip.

\subsection{Spares, reserved}

 \begin{pinout}{chip-reserved}{2}{Reserved}
	\pin{\In}{Esc0}{Escape0}
	\pin{\In}{Esc1}{Escape1}
 \end{pinout}

The behavior of the \chip\ is characterized only when the two pins
{\sym Escape0} and {\sym Escape1} are tied to logical 0.

In some versions of the die used for the \chip, for fabrication
convenience some of the spare die area may have been used for other chips.
A scheme presently being considered for this multiplexing of
functions on the same die is the following
 \begin{equation}\label{eq.chip-mode}
 \begin{tabular}{|cc|p{1.25in}|}\hline
	\sym Esc0 & \sym Esc1 & \multicolumn{1}{c|}{chip selected}\\\hline\hline
	0 & 0 & \chip\\
	0 & 1 & {\sc ctlsv} chip\\
	1 & 0 & {\sc fsm} chip\\
	1 & 1 & {\sc dataregs} chip\\\hline
 \end{tabular}\;.
 \end{equation}
	The \cam\ controller will use one {\sc fsm}, two {\sc stlsv},
and two {\sc dataregs} chips.

\endinput




\addtocounter{footnote}{-1}\footnotetext
	{Since we use nybble-wide chips, total \dram\ capacity with 11
address lines is $2^{2\cdot 11}\cdot 4$, or 16M bits.}
\addtocounter{footnote}{1}\footnotetext
	{Once we are in fast-page or static-column mode, typically a
\dram\ read/write operation takes 4 clock cycles; in the first two, a
nybble is read, in the second, a nybble is written.}
