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\chapter{\chip{} Registers}\label{sect.regs}

This chapter systematically presents (see \cf{chip-regs} for an
overview) the registers that make up the \chip\ {\em register address
space}. This address space is directly accessible by the \bus. Other
on-chip data structures are accessed only in an indirect way (for
instance, the {\sym Event Counter} is read by the user via a register
called the {\sym Event Count Register}), or are of no immediate
relevance to the \step{} user.

Each register is presented in a separate section; the section number
itself (e.g., the `\ref{sample-section}' in \sect{MIDR})
coincides with the register's address (\sect{chip-regs}). The makeup
of each register is summarized in tabular form immediately below the
section title. The register's length in bits is given, followed by the
register's mnemonic and its full name.  Often, a register is actually
a collection of logically separate components; in such cases the
components themselves are individually listed, starting from the one
at the least-significant-digit end of the register. For example, the
30 bits of the {\sym Kick Register} (\sect{KR}) comprise a
24-bit {\sym Kick Amount} (whose least significant bit is the
least significant bit of the entire {\sym Kick Register}), three
one-bit {\sym Kick Sign}s, and three one-bit {\sym Kick Max Flag}s.
This listing order corresponds to the order in which bits are
transmitted to or received from a register, i.e., least-significant
bit first.

All registers are both readable and writable, although most would only
be read for error recovery or test purposes.  At power-on reset, all
registers except the {\sym Module ID Register} are cleared to zero
(see \sect{MIDR}); a host-initiated, {\em soft}, reset is similar, but
leaves the DRAM contents and several registers ({\sym OSR}, {\sym IR}
and {\sym DOCR}) unchanged.

As mentioned in \sect{chip-regs}, the two I/O registers, namely the
{\sym Scan I/O Register} and the {\sym LUT I/O Register}, follow their
own conventions concerning length of transfers.  Moreover, the {\sym
Event Count Register}, whose full length is 25 bits, may be
read or written for only part of its length, as specified by the {\sym
Event Counter Length} component of the {\sym Scan Format Register}.

\medskip

For reference, a summary description of \step{} registers is given
immediately below; detailed descriptions follow.



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\setcounter{section}{-1}
\section{Module Select Register}\label{sect.MSR}

 \begin{register}{\ \ 3}{MSR}{Module Select Register}
 \end{register}%
	 In order for a \step{} module to be enabled to accept the data
broadcast by the host on the \bus\ during a write frame or put its own
data on the \bus\ during a read frame, the module must be {\em
selected}, as explained in \sect{modselect}. The parameters upon which
this selection depends are specified by a three-bit {\em selection
code} written to the {\sym Module Select Register}.  Selection codes
(see table \eq{selection-codes.rpt}) specify which internal register
should match which target value. For the selection to be successful.
all \chip{}s in the module must simultaneously indicate a match
between their selected registed and their target.

 \begin{equation}\label{eq.selection-codes.rpt}
 \input selection-codes.insert
 \end{equation}

Owing to its special role in the selection mechanism, the {\sym Module
Select Register} ``escapes selection,'' in the sense that data {\em
written} to it by the \bus\ are accepted by {\em every} module
regardless of the module's current selection status.  The selection
status of a module (i.e., selected or not) is latched when this
register is written, and remains in force until this register is
written again.

The {\sym Module Select Register} also escapes normal selection on
reads: read operations require a single module to be selected, and so
the normal selection mechanism wouldn't allow us to read back the
current selection status of \step{} if more than one module happened to
be currently selected!  Since the {\sym Module Select Register}s of
all modules are always written simultaneously, it doesn't matter {\em
which} module responds to a read of the {\sym MSR}, as long as only
one does: a bit in the {\sym Hardware Environment Register}
(\sect{HER}) is used to single out one particular module for this
``honor.''


\section{Run Mode Register}\label{sect.RMR}

\begin{register}{\ \ 6}{RMR}{Run Mode Register}
	\compositeof
	\subreg{2}{SSM}{Scan Sync Mode}
	\subreg{1}{RT}{Run Type}
	\subreg{1}{ECT}{Event Count Transfer}
	\subreg{1}{RPK}{Repeat Previous Kick}
	\subreg{1}{ALT}{Active LUT Toggle}
 \end{register}%
	Writing a nonzero value to the {\sym Scan Sync Mode} {\em
schedules} a scan (\cf{scanner}), i.e., instructs the \chip\ to start
a new scan as soon as possible; the specific value written in the
register determines to what extent the scan itself and the individual
sweeps that make it up must be synchronized---as detailed in table
\eq{scan-sync-mode}---with the {\sym VCAM} and {\sym HCAM} pulses that
travel on the \bus\ {\sym Sync} line (\sect{sync-signal}). At the end
of the scan, this register is automatically cleared.

 \begin{equation}\label{eq.scan-sync-mode}
 \begin{tabular}{|c|p{2.25in}|}\hline
	\sym SSM & \multicolumn{1}{c|}{Scan Sync Mode}\\\hline
	0 & \parhead{Standby} No scan scheduled. \\
	1 & \parhead{Frame sync} The starting of individual sweeps of
the scan will wait for a horizontal sync pulse, {\sym HCAM}; the
first sweep of the scan (and thus the entire scan) will wait for a
vertical sync pulse, {\sym VCAM} (which also acts as an {\sym
HCAM} pulse).  \\
	2 & \parhead{Line sync} Individual sweeps of the scan will
wait for {\sym HCAM}. {\sym VCAM} is treated as equivalent to
{\sym HCAM} \memo{check this}.\\
	3 & \parhead{Free run} The scan will start immediately, 
and sweeps will follow one another without any gaps.\\\hline
 \end{tabular}
 \end{equation}
	The {\sym HCAM} and {\sym VCAM} pulses appear on the same
\bus\ {\sym Sync} line (\sect{bus-signals}) on which the {\sym HMON}
and {\sym VMON} pulses appear, and are in a definite phase
relationship with them. The latter are sent to the {\sc crt} monitor
to which video data are fed (\sect{DSR}). Thus, in a scan of sync mode
1 a sector may be scanned in lockstep with the scanning of the {\sc crt}
monitor.
	A sync mode 2 scan typically consists of a single sweep; this is
used when one intends to change some of the registers (e.g., the {\sym
Kick Register}) from one sweep to the next.
	A sync mode 3 scan, in which the timing of the scanning is not
constrained by real-time display considerations, yields, of course,
the fastest scanning rate.

\medskip

In all cases, the actual start of each sweep is shifted in time by the
amount specified by the {\sym Tree Balancing Delay} (\sect{HER}), to
insure that modules placed at different distances from the \bus\ root
will all scan in lockstep (\cf{tree-balancing}).

\medskip

The {\sym Scan-in-Progress} signal is defined as the logical {\sc or}
of the two bits of the {\sym Run Mode Register}, and has a value of 1
from the moment a scan is scheduled to the moment the scan itself
ends. This signal is made available to the \step{} interface via the
{\sym Status} line (\cf{bus-signals}, \sect{SFR}), to allow the
interface to determine when a scan is finished, and thus when
operations that must wait for end-of-scan (such as the
scheduling of a new scan) can proceed.

\medskip

Although the {\sym Run Mode Register} isn't double buffered, the delay
between the end of one scan and the beginning of the next need not be
longer than a few cycles. In fact, the data to be sent to this
register to schedule a new scan can be loaded into the \step{}
interface during the current scan, ready to be broadcast to the \step{}
modules as soon as the {\sym Scan-in-Progress} signal is no longer
asserted (\cf{cam-wait}). (As explained in \sect{ECR}, the event
counts for the current scan are double-buffered and can be read at
leisure {\em after} the new scan has started.)

\medskip

Several other actions associated with scheduling a scan are controlled
by the {\sym Run Mode Register}, and occur (if indicated) when this
register is written.

The {\sym Run Type} is used to label a scan with some extra ``type''
information (one bit per \chip).  This information is made visible to
external hardware during the scan via multipurpose pins (see
\sect{MPCR}, {\sym Run Type}).  The {\sym Run Type} is then reset to
zero at the end of the scan.  If, for example, a Frame Buffer is
attached to the CAM display, and a multipurpose pin is configured
appropriately, we could signal which scans should be captured for
display by appropriately setting a {\sym Run Type} bit whenever we
write the {\sym Run Mode Register}.

The {\sym Event Count Transfer} bit controls whether to copy the value
accumulated in the {\sym Event Counter} (over perhaps several scans)
into the {\sym Event Count Register}.  Whenever a transfer occurs, the
{\sym Event Counter} itself is automatically cleared.  Thus, as we
start a new scan, the count from the previous scan can be made
available to be read back by the host during the new scan
(\sect{ECR}).

The {\sym Repeat Previous Kick} bit is an optimization.  Normally, the
{\sym Offset Register} is decremented by the {\sym Kick Amount}
whenever the {\sym Kick Register} is written.  If the kick for the
next scan is the same as that just used, we can avoid rewriting the
{\sym Kick Register} by simply reusing its current value, and again
decrementing the offset.  Note that if we want a kick of zero, we must
explicitly change the kick to zero (by writing the {\sym Kick
Register}); it is not enough to simply fail to set the {\sym Repeat
Previous Kick} bit.

Special care must be taken when the scanning of a sector is broken up
into several subscans. Kicks sent (or repeated) on each subscan would
accumulate, which usually is not what we want. On the other hand,
sending a kick of zero for all subscans except the first would produce
the right results as far as the offset is concerned, but would deprive
the gluing machinery of the relevant information.  The correct
approach when gluing is involved is, before each subscan after the first,
to ``undo'' the previous kick (by sending its complement) and then
send the desired kick afresh.


The {\sym Active LUT Toggle} switches the roles of {\em active} and
{\em inactive} \lut\ between \lut\ 0 and \lut\ 1.  The active \lut\ is
the one that will be used as the main processing element in the data
stream (cf.\ \fig{style-block}).  The other, or inactive, \lut\ is
accessible to the \bus\ via the {\sym LUT I/O Register} (\cf{LIR});
specifically, it can be loaded with new contents even while a scan is
in progress (\cf{bus-usage}).

One can find out which of the two \lut{}s is the active one by reading
the {\sym Active LUT Select} bit in the {\sym Hardware Environment
Register} (\sect{HER}). By writing that bit, one can force a specific
\lut\ (rather than just ``the other one'') to be the active one.


\section{Kick Register}\label{sect.KR}

 \begin{register}{\ 30}{KR}{Kick Register}
	\compositeof
	\subreg{24}{KA}{Kick Amount}
	\subreg{1}{XKS}{X-Kick Sign}
	\subreg{1}{YKS}{Y-Kick Sign}
	\subreg{1}{ZKS}{Z-Kick Sign}
	\subreg{1}{XKMF}{X-Kick Max Flag}
	\subreg{1}{YKMF}{Y-Kick Max Flag}
	\subreg{1}{ZKMF}{Z-Kick Max Flag}
 \end{register}%

The basic philosophy of ``kicking'' is explained in \sect{kicking}.

The bits of the {\sym Kick Amount} constitute a $d$-component vector,
$\vec{k}$, representing a displacement in a $d$-dimensional space.
The structure of this vector (number $d$ of components and number of
bits devoted to each component) is determined by the {\sym Dimension
Register}, as explained in \sect{dimensions}. As soon as it is sent,
this vector is subtracted from the {\sym Offset Register}
(\sect{OSR})---another vector with the same structure which keeps
track of the current position of the origin of coordinates of \step{}
space. 

Subtraction of the {\sym Kick Amount} from the {\sym Offset Register},
and, in general, all site-address arithmetic is performed
independently on the separate site-address slices determined by {\sym
Dimension Cut Mask} in the {\sym Dimension Register}. Each slice of
the {\sym Kick Amount} specifies the size of the kick for the
corresponding dimension. For the three extendible dimensions $x$, $y$,
and $z$ the {\sym Kick Amount} is further qualified by a {\sym Kick
Sign} and a {\sym Kick Max Flag}; the information contained in all
three registers is used {\em during a scan} by the glue machinery.

\medskip

If $n$ is the number of site address bits assigned to a certain
dimension by the {\sym Dimension Cut Mask} (cf.\
\fig{dimension-cuts}), then the {\sym Kick Amount} for that dimension
ranges from 0 thru $2^n-1$ ($2^n$ distinct choices).

For each of the three extendible dimensions, the corresponding {\sym
Kick Amount} component is extended by a {\sym Kick Sign} bit and a
{\sym Kick Max Flag} bit. With the help of these two bits, the range
of the kick is extended to the interval [$2^{-n}$,$2^{+n}$] (overall,
$2^{n+1}+1$ distinct choices).  Jointly, {\sym Kick Amount} and {\sym
Kick Sign} express the value of the kick in two's complement notation,
from $2^{-n}$ through $2^{+n}-1$ (i.e., $2^{n+1}$ choices).  The last
value of the interval, namely $2^{+n}$, is distinguished from the
value of 0 by writing a 1 in the {\sym Kick Max Flag}.

In the following discussion, we'll use, for definiteness, $n=8$.
Then the {\sym Kick Amount} component ranges from {\tt 00} to {\tt FF}
(in hex). A kick of {\tt 01} will circularly shift (within the sector
boundaries) the layer's data by one position in the positive
direction; a kick of {\tt FF} will shift the data by 255 positions in
the positive direction, or, which is equivalent, by one position in
the negative direction.

For each of the three extendible dimensions, the shift specified by
the {\sym Kick Amount} affects the layer as a whole (rather than each
sector being independently circularly shifted), and the {\sym Kick
Sign} is used as the most significant bit in the two's complement
notation.  One obtains in this way a kick range from $-256$ to +255;
the value +256 is also possible using only data from nearest
neighboring modules, and is indicated by setting the corresponding
{\sym Kick Max Flag}.  The entire range of cases, for an 8-bit
slice, is summarized by the following table (using the $x$ dimension
for definiteness)
 \begin{equation}\label{eq.kick-range}
 \begin{tabular}{|c|c|c|r|}\hline
	\sym XKMF & \sym XKS & \sym KA &\\
	Max flag & sign & amount & \multicolumn{1}{c|}{Actual
shift}\\\hline
	1 & 0 & \tt 00 & +256\\
	0 & 0 & \tt FF & +255\\
	0 & 0 & \tt FE & +254\\
	$\vdots$ & $\vdots$ & $\vdots$ & $\vdots$ \\
	0 & 0 & \tt 02 & +2\\
	0 & 0 & \tt 01 & +1\\
	0 & 0 & \tt 00 & 0\\
	0 & 1 & \tt FF & $-1$\\
	0 & 1 & \tt FE & $-2$\\
	$\vdots$ & $\vdots$ & $\vdots$ & $\vdots$ \\
	0 & 1 & \tt 02 & $-254$\\
	0 & 1 & \tt 01 & $-255$\\
	0 & 1 & \tt 00 & $-256$\\\hline
 \end{tabular}
 \end{equation}

Note that if the {\sym Kick Sign} and {\sym Kick Max Flag}s are both
fixed at zero, and the {\sym Dimension Cut Pointer}s (\sect{DR}) are
set appropriately (a value of 31), then $x$, $y$, and $z$ can be used
as internal dimensions: they will be internally wrapped around and no
use will be made of glue.


\section{Site Address Bit Select Register}\label{sect.SABSR}

 \begin{register}{\ \ 5}{SABSR}{Site Address Bit Select Register}
 \end{register}%
	This register selects one of the {\sym Site Address}'s 24 bits
as part of the data to be sent to a given destination, when source 3
is selected (\cf{source-dest}).
	Specifically, routing site-address information to the lookup
table is one way to make the dynamics {\em space}-dependent.


\section{LUT Address Source Register}\label{sect.LASR}

 \begin{register}{\ \ 6}{LASR}{LUT Address Source Register}
	\compositeof
	\subreg{2}{LAS}{LUT Address Select}
	\subreg{4}{LAM}{LUT Address Map}
 \end{register}%

{\sym LUT Address Select} and {\sym LUT Address Map} are used to
construct the source for the LUT Address destination signal
(\cf{source-dest}).


\section{Flywheel Output Source Register}\label{sect.FOSR}

 \begin{register}{\ \ 6}{FOSR}{Flywheel Output Source Register}
	\compositeof
	\subreg{2}{FOS}{Flywheel Output Select}
	\subreg{4}{FOM}{Flywheel Output Map}
 \end{register}%

{\sym Flywheel Output Select} and {\sym Flywheel Output Map} are
used to construct the source for the Flywheel Output
destination signal (\cf{source-dest}).


\section{Site Data Source Register}\label{sect.SDSR}

 \begin{register}{\ \ 6}{SDSR}{Site Data Source Register}
	\compositeof
	\subreg{2}{SDS}{Site Data Select}
	\subreg{4}{SDM}{Site Data Map}
 \end{register}%

{\sym Site Data Select} and {\sym Site Data Map} are used to construct
the source for the Site Data destination signal (\cf{source-dest}).


\section{Event Counter Source Register}\label{sect.ECSR}

 \begin{register}{\ \ 6}{ECSR}{Event Counter Source Register}
	\compositeof
	\subreg{2}{ECS}{Event Counter Select}
	\subreg{4}{ECM}{Event Counter Map}
 \end{register}%

{\sym Event Counter Select} and {\sym Event Counter Map} are used to
construct the source for the Event Counter destination signal
(\cf{source-dest}).


\section{Display Source Register}\label{sect.DSR}

 \begin{register}{\ \ 6}{DSR}{Display Source Register}
	\compositeof
	\subreg{2}{DDS}{Display Data Select}
	\subreg{4}{DDM}{Display Data Map}
 \end{register}%
	The {\sym Display Source Register} controls the relationship
of the \step{} unit to a dedicated video display, and also controls
which data is read back during a scan \io\ operation (\cf{SIOR}).
    
\medskip

The {\sym Display Data Select} and the {\sym Display Data Map} are
used to construct the source for the Display Data destination signal
(\cf{source-dest}).

Note: Display Data signals output a value of zero during any clock
when there is no valid display bit available.


\section{Show Scan Register}\label{sect.SSR}

\begin{register}{\ \ 1}{SSR}{Show Scan Register}
 \end{register}%
	The \step{} interface must wait for an end-of-scan condition
before it proceeds to read or write a register involved in the scan.
Since it is possible that not all modules are performing identical
scans (e.g., one distinguished module may be acting as a frame
buffer), we explicitly choose which module is to provide feedback on
the state of the scan.  Note that, on the selected module, this
information is normally combined with the {\sym Interrupt} signal
coming from outer modules to produce the {\sym Status} signal.

More specifically, when {\sym Show Scan} is set, the {\sym
Scan-in-Progress} signal generated by the \chip\ (\sect{RMR}) is
multiplexed onto the \bus\ {\sym Status} line, which also carries the
\bus\ {\sym Interrupt*} signal: the {\sym Scan-in-Progress} signal is
chopped ({\sc and}ed with a signal that toggles at the clock rate),
inverted, and {\sc and}ed with {\sym \bus\ Interrupt*}.


\section{Event Count Register}\label{sect.ECR}

 \begin{register}{-{}-{}-}{ECR}{Event Count Register}
 \end{register}%
	The {\sym Event Count Register} is used as a buffer for the
\chip's event counter (\sect{event-counter}), to permit reading the
count from the previous scan even as a new count is accumulating
during the current scan.  It has the same physical length of 25 bits
as the event counter, and is loaded with the contents of the latter at
the moment that the {\sym Run Mode Register}'s {\sym Event Count
Transfer} bit is set (\sect{RMR}).

\medskip

The event count is the most likely quantity that will be read from all
modules at possibly frequent intervals during a simulation.  Two
provisions are made to optimize this readback.

With short scans, new event counts will be available with
great frequency;\footnote
	{In fact, short scans are usually set up in order to
measure totals or averages separately over small patches of space
rather than over an entire sector.}
	on the other hand, in this situation the maximum possible
value recorded by the event counter will be small, so that the
effectively used length of this counter may reduce to just a few bits.
The {\sym Event Counter Length} (\sect{SFR}) specifies this effective
length, instructing the \chip\ to transmit only that many bits during
the read-out of the {\sym Event Count Register}.  Note that registers
are read by circularly shifting their contents past an output tap;
when less than 25 bits are read from this register, the data will be
left in the register with a different alignment than before the read
operation. If a reread of the same data is desired, one must be aware
of the new alignment.

By making use of the sequential-read mode (\sect{sequential-read}),
it is possible to read all event counters in a single \bus\ frame,
with automatic switchover of bus control from one module to the next.
This allows all event counters to be read without repeatedly changing
bus direction to explicitly select each module in turn.

Although the {\sym Event Count Register} is normally only read, like
all other registers it can also be written.  To facilitate testing,
when this register is written, the same value is also written into the
event-counter itself.  Reading this register or performing a verify
write on it leaves the counter unaffected.


\section{LUT Index Register}\label{sect.LIR}

 \begin{register}{\ 16}{LIR}{LUT Index Register}
 \end{register}%
	The {\sym LUT Index Register} indicates which entry of the
inactive \lut\ (\sect{RMR}) is to be accessed. The pointer
autoincrements each time an entry is read or written, thus pointing to
the next entry to be accessed.  A data transfer to this register is
presumed to be finished when the pointer increments to zero.

The same register does double duty in a different context.  When event
counters are read back in sequential-read mode (\sect{ECR},
\sect{sequential-read}), the {\sym LUT Index Register} provides the
target name specifying which module is to be selected in turn.  The
pointer autoincrements each time {\sym Event Count Length} number of
bits have been read, thus pointing to the next module to be selected.

In principle, each \chip\ is responsible for only one bit of the
pointer. For both hardware convenience and increased flexibility, the
entire counter is repeated within each \chip, and each chip of a set
is instructed by its {\sym LUT Index Permutation Register}
(\sect{LIPR}) to use a different bit of this counter.


\section{LUT Index Permutation Register}\label{sect.LIPR}

 \begin{register}{\ \ 5}{LIPR}{LUT Index Permutation Register}
 \end{register}%
	As mentioned in \sect{LIR}, each \chip\ has its own copy of
the entire {\sym LUT Index Register} but uses only one bit of it. The
{\sym LUT Index Permutation Register} specifies which of the {\sym LUT
Index Register}'s 16 bits is to be used by a given \chip\ during table
downloading.

Normally, \chip\ 0 will use the bit in position 0, \chip\ 1 that in
position 1, etc., to compose the load address.  However, it is
possible to specify a different correspondence between \chip{} numbers
and bit positions.  This feature can be used to download a given table
with the roles of its inputs permuted.  One can also bypass the
{\sym LUT Index Register} and send instead a constant of 0 or 1.  This
feature is used to download a specified portion of the \lut.

The available choices are summarized in the following table
 \begin{equation}\label{eq.lppr-choices}
 \begin{tabular}{|l|l|}\hline
	{\sym LIPR} & \multicolumn{1}{|c|}{\sym \lut\ address bit source}\\\hline\hline
	$\phantom{0}$0 & bit $\phantom{0}$0 of {\sym LUT Index Register}\\
	$\phantom{0}$1 & bit $\phantom{0}$1 of {\sym LUT Index Register}\\
	$\phantom{0}$2 & bit $\phantom{0}$2 of {\sym LUT Index Register}\\
	$\phantom{0}$$\vdots$\ & \quad$\vdots$\\
	15 & bit 15 of {\sym LUT Index Register}\\ \hline
	16--29 & not used\\\hline
	30 & 0\\
	31 & 1\\\hline
 \end{tabular}\
 \end{equation}

  
\section{LUT I/O Register}\label{sect.LIOR}

 \begin{register}{-{}-{}-}{LIOR}{LUT I/O Register}
 \end{register}%
	As mentioned in \sect{chip-regs}, the {\sym LUT I/O
Register} is used for writing data to the inactive \lut\
(\sect{RMR}) or reading data from it, and does not have an
intrinsic length.

The data transfer starts from the location initially specified by the
{\sym LUT Index Register} (\sect{LIR}), which will have been set up
previously, and continues upwards (this pointer is autoincrementing).
The transfer ends when the {\sym LUT Index Register} reaches its
terminal count; whereupon, on a read frame the \chip\ quits sending
bits, while on a write frame it signals an error by setting the {\sym
Register Length Interrupt Flag} (\cf{IR}) if additional bits are
received.  After an error-free transfer the {\sym LUT Index Register}
contains a value of zero.

\medskip

If the {\sym Verify Write Flag} (\sect{VWR}) is set, any portion of
the inactive \lut\ may of course be checked instead of written.  Note
that, unlike all other registers, it is not possible to use the verify
write mode to perform {\em write-per-bit} (see \sect{VWR}) to the {\sym LUT
I/O Register}.


\section{Scan Index Register}\label{sect.SIR}

 \begin{register}{\ 24}{SIR}{Scan Index Register}
 \end{register}%
	The {\sym Scan Index Register} is an autoincrementing pointer
which specifies the sequential place, within a scan, of the currently
accessed site.  At the beginning of an experiment this pointer will
normally be initialized by writing a value of 0 to it.  Since the
length of a scan is always a power of two (see {\sym End-of-Scan
Pointer}, \sect{SFR})---say, $2^n$---the $n$ low-order bits of
the {\sym SIR} will return to zero at the end of each scan. Thus, this
register does not ordinarily need to be cleared between scans.

Since the {\sym SIR} ultimately points to a \dram\ bit
(cf.\ \fig{scanner}), its clocking
rate is geared to the accessibility of that bit as a source and/or a
destination; on data transfers between the host and \step, it is
further constrained by the accessibility of the corresponding host
bit.  In the fastest scanning modes (modes 2 and 3 in \sect{SFR}), the
{\sym SIR} peak clock rate equals the system clock rate; in modes 0
and 1, it drops to one quarter that rate (since only one bit per
\dram\ nybble is effectively usable).  During host \io\ via the {\sym
Scan I/O Register}, operation of the scan circuitry (including the
{\sym Scan Index Register}) is enabled by the \bus\ handshake signals
(\cf{data-readiness}).
 
\section{Scan Index Permutation Register}\label{sect.SIPR}

 \begin{register}{120}{SIPR}{Scan Index Permutation Register}
	\compositeof
	\subreg{5}{SSA0}{Select Site Address \ 0}
	\subreg{5}{SSA1}{Select Site Address \ 1}
	\subreg{}{\ .}{}
	\subreg{}{\ .}{}
	\subreg{}{\ .}{}
	\subreg{5}{SSA23}{Select Site Address 23}
 \end{register}%
	As explained in \sect{scan-permuter}, the order in which sites
are accessed during a scan is derived from the {\sym Scan Index
Register}, which is incremented by one for each scanned site. When the
24 scan index bits are directly used in their natural order as site
address bits, then the entire module is scanned as if by series of
nested loops in which the first dimension corresponds to the innermost
loops and the last to the outermost loop (\cf{dimensions},
\sect{DR}).

However, this order can be significantly altered by permuting the scan
index bits before using them as site address bits.  The source of each
of the 24 site address bits is specified by the value of a five-bit
{\sym Select Site Address $n$} pointer\footnote
	{These registers actually allow one to have all possible {\em
combinations with repetition}, of which permutations form a subset.
In practice, however, permutations are all that we are generally
interested in.}
	according to the following table
 \begin{equation}\label{eq.permuters-choices}
 \begin{tabular}{|l|l|}\hline
	\sym SSA & \multicolumn{1}{|c|}{site-address bit
source}\\\hline\hline
	$\phantom{0}$0 & bit $\phantom{0}$0 of the {\sym Scan Index Register}\\
	$\phantom{0}$1 & bit $\phantom{0}$1 of the {\sym Scan Index Register}\\
	$\phantom{0}$2 & bit $\phantom{0}$2 of the {\sym Scan Index Register}\\
	$\phantom{0}$$\vdots$\ & \quad$\vdots$\\
	23 & bit 23 of the {\sym Scan Index Register}\\\hline
	24--29 & not used\\\hline
	30 & 0\\
	31 & 1\\\hline
 \end{tabular}\;.
 \end{equation}
	Note that the constant values 0 and 1 are among the possible
sources.  This is important for scanning less than the whole space: in
this case the unused address bits are set to a constant that specifies
which part of the space is being scanned (\cf{scanner}).


\section{Scan I/O Register}\label{sect.SIOR}

 \begin{register}{-{}-{}-}{SIOR}{Scan I/O Register}
 \end{register}%
	 As mentioned in \sect{chip-regs}, the {\sym Scan I/O
Register} is used for accessing all or part of the \dram\ chip
connected to a given \chip, and does not have an intrinsic length.  By
setting up a scan of a certain size and shape (see \sect{SFR}),
data may be read from or written to the scanned area through the {\sym
Scan I/O Register}.

Addressing the
{\sym Scan I/O Register} starts a scan\footnote
	{At the moment of initiating a \dram\ \io\ operation via this register,
the {\sym Scan Sync Mode} (\sect{RMR}) will normally be found to be 0,
indicating that no internally-clocked scan is in progress or scheduled;
nevertheless, typically one will explicitly write to it before
performing \dram\ \io, in order to transfer the event count from the
previous scan into the {\sym Event Count Register}.}
	that is clocked by data transfer across the \bus\ (\cf{SIR}).
By appropriately setting the {\sym Source Register}s
(\sect{LASR}--\sect{ECSR}), host-generated data may be integrated into
this \bus-driven scan.  This not only allows host data to be combined
with current \dram\ data, but, depending on the options selected, it
also allows the host to do read/write operations that are not associated with
scanned sites. For example, the host can write to the event counter
(for testing), or put data on the video bus so as to
download a new color palette to the \crt\ interface (\cf{}). In a
similar way, a \bus\ read transaction with the {\sym Scan I/O
Register} makes a module scan (and possibly update) its data with a
timing that takes into account the \sbus's moment-by-moment availability
to accept data.  All {\sym Scan I/O} read operations get their data
from what is fed to the Display Data destination (\cf{DSR}).

\medskip

If the {\sym Verify Write Flag} (\sect{VWR}) is set, any portion of
the \dram\ may of course be checked instead of written.


\section{Scan Format Register}\label{sect.SFR}

 \begin{register}{\ 35}{SFR}{Scan Format Register}
	\compositeof
	\subreg{2}{SM}{Scan Mode}
	\subreg{5}{ESC}{End-of-Scan}
	\subreg{4}{ESW}{End-of-Sweep}
	\subreg{4}{EST}{End-of-Stretch}
	\subreg{5}{SBRC}{Sweeps Between Refresh Cycles}
	\subreg{8}{RCL}{Refresh Cycle Length}
	\subreg{5}{ECL}{Event Counter Length}
	\subreg{2}{STM}{Stretch Magnification}
 \end{register}%
	The {\sym Scan Format Register} is used, in conjunction with the
{\sym Scan Index Permutation Register}, to set the scan format.

The {\sym Scan Mode} selects one of the four basic scan modes: mode 0
(open sweep, no row break), mode 1 (closed sweep, no row break), mode
2 (open sweep, 1 row break allowed), mode 3 (closed sweep, 1 row break
allowed).  These modes are explained in detail in \sect{}--\baresect{}.
The software should select the fastest of these four modes of scan
that is compatible with the selected permutation (allowing a row break
adds overhead to the scan, even if no row break actually occurs).  All
chips operating in the same mode with the same format parameters are
guaranteed to have the same scan timing.

The {\sym End-of-Scan} holds the log (to base two) of the length of
the scan: the number of updates that each module will perform without
waiting for further instructions from the host (\cf{}).  The hardware
derives its end-of-scan signal by using this value as a pointer to a
carry position in the {\sym Scan Index Register}.

Similarly, {\sym End-of-Sweep} determines the length of accesses that
the hardware should assume lie within a single \dram{} row, and {\sym
End-of-Stretch} determines the number of bits that the hardware can
assume will be accessed from consecutive locations.  As with {\sym
End-of-Scan}, the actual {\em End} signal is derived by interpreting
these values as pointers to carry positions within the {\sym Scan
Index Register}.

{\sym Sweeps Between Refresh Cycles} is the number of sweeps to
perform between each refresh cycle; the {\sym Refresh Cycle Length}
indicates the number of refreshes to perform during each refresh cycle
(refreshes are continuously performed when scanning isn't taking
place).

The {\sym Event Counter Length} specifies the effective length of the
event counter, which may be less than 25 bits (see \sect{ECR}).  This
length will depend on the number of sites to be counted between
readings, and typically is set whenever the scan size is changed.

The {\sym Stretch Magnification} is used when the {\sym Scan Index
Permutation Register} is configured to achieve a readback or display
with magnification (i.e., zoom).  Up to a factor of 4, this value is
the log of the magnification -- above 4 it should have a value of 3.
The {\sym Stretch Magnification} applies only to the component of the
magnification that affects the stretch, and is needed by the DRAM
address control circuitry to set up the nibble access pattern.


\section{Offset Register}\label{sect.OSR}

 \begin{register}{\ 24}{OSR}{Offset Register}
 \end{register}%
	As explained in \sect{}, the {\sym Offset Register} of a
\chip\ records (modulo the size of each dimension) by how much the
origin of the associated layer has shifted with respect to its
initial reference position under the cumulative action of previous
kicks.

\medskip

The layer offset is added (separately for each dimension, as specified
by the {\sym Dimension Cut Mask}, \sect{DR}) to
the site address (which normally is the same for all layers) to yield
the {\sym Physical Address} (in \dram) of the bit belonging to the
currently scanned site and to the layer in question.

To implement the gluing algorithm (\sect{}), this \dram\ bit is made
available to the data stream (\sect{}) together with the homologous
bits coming from the six adjacent modules.  Which of these six bits is
actually used depends on the $x$, $y$, and $z$ carries from the above
addition, in conjunction with the corresponding kick signs
(\sect{KR}).

\medskip

The {\sym Offset Register} is not cleared by a soft
(interface-initiated) \chip-reset.  This is done to facilitate error
recovery (see {\sym IR} and {\sym DOCR}).

\section{Dimension Register}\label{sect.DR}

 \begin{register}{\ 38}{DR}{Dimension Register}
	\compositeof
	\subreg{23}{DCM}{Dimension Cut Mask}
	\subreg{5}{XDCP}{X-Dimension Cut Pointer}
	\subreg{5}{YDCP}{Y-Dimension Cut Pointer}
	\subreg{5}{ZDCP}{Z-Dimension Cut Pointer}
 \end{register}%
	The {\sym Dimension Register} is used to indicate how the
simulation space is shaped into a multidimensional array.

\medskip

Specifically, the 23-bit {\sym Dimension Cut Mask} is used
to cut the site-address arithmetic chain into up to 24 slices, each
corresponding to a distinct dimension (\cf{dimensions}).

The {\sym X-Dimension Cut Pointer} specifies which of those dimensions
is to be identified with the extendible dimension $x$. As indicated in
the following table
 \begin{equation}\label{eq.xcut-choices}
 \begin{tabular}{|l|l|}\hline
	{\sym XDCP} & \multicolumn{1}{|c|}{{\sym X-Wrap} source}\\\hline\hline
	$\phantom{0}$0 & carry from bit $\phantom{0}$0\\
	$\phantom{0}$1 & carry from bit $\phantom{0}$1\\
	$\phantom{0}$2 &  carry from bit $\phantom{0}$2\\
	$\phantom{0}$$\vdots$\ & \quad$\vdots$\\
	23 &  carry from bit 23\\\hline
	24--29 & not used\\\hline
	30 & 0\\
	31 & 1\\\hline
 \end{tabular}\;,
 \end{equation}
	this pointer selects, as the source for the {\sym X-Wrap}
signal, the borrow (out of the corresponding slice) resulting from
subtracting the $x$-component of the kick from the $x$-component of
the site address. Values 30 and 31 of the {\sym Dimension Cut
Pointer}s substitute for this borrow a constant value of 0 or 1; this
is useful for testing, or for suppressing external gluing and allowing
an extendible dimension to be wrapped around within the module
(\cf{KR}).

Analogous considerations apply to the $y$ and $z$ dimensions and the
associated {\sym Dimension Cut Pointer}\,s.  Note that external gluing
is controlled by the {\sym Kick Sign}s and {\sym Kick Max Flag}s, as
well as by the {\sym Cut pointers}.
 

\section{Hardware Environment Register}\label{sect.HER}

 \begin{register}{\ 16}{HER}{Hardware Environment Register}
	\compositeof
	\subreg{1}{LPL}{LUT Pipeline Length}
	\subreg{1}{FPL}{Flywheel Pipeline Length}
	\subreg{1}{DCS}{DRAM Column Size}
	\subreg{6}{TBD}{Tree Balancing Delay}
	\subreg{4}{TMS}{Test Mode Select}
	\subreg{1}{NBF}{Node Bypass Flag}
	\subreg{1}{SRE}{Select Read Enable}
	\subreg{1}{ALS}{Active LUT Select}
 \end{register}%
	The {\sym Hardware Environment Register} contains information
about the hardware connected to the \chip: the size of the \dram, the
configuration of the \bus, pipelining information about the updating
circuitry, etc.

If the {\sym LUT Pipeline Length} is set, five bits of pipeline
delay are expected between the \sram\ address pins and the \sram\ data
pins (\sect{dram-side-pins}); otherwise, only one bit of delay is
expected.  What is normally connected between these two sets of pins
is a \sram\ lookup table which operates in a single clock cycle.

Similarly, if the {\sym Flywheel Pipeline Length} is set, five bits
of pipeline delay (rather than one) are expected in any hardware
connected between the flywheel data output pins and the flywheel data
input pins (\sect{flywheel-pins}).

\medskip

The \chip\ can work with \dram{}s with two column address sizes: 10
bits or 11 bits.  4 Mbit, nibble-wide \dram{}s have a 10 bit column
address and a 10 bit row address (10+10); 16 Meg \dram{}s come in both
10+12 and 11+11. The {\sym DCS} bit is used to tell the chip the width
of the column address, according to the following table
 \begin{equation}\label{eq.dram-size}
 \begin{tabular}{|c|c|r|}\hline
	\sym DCS & column\ address\ width \\\hline\hline
	0 & 10 \\
 	1 & 11 \\\hline
 \end{tabular}.
 \end{equation}
	In the 10-bit mode, for chip test purposes, the two unused
column-address lines carry the two least significant bit of the
\dram{} address, i.e., the address bits that select a bit within a
nibble.

If the \bus\ tree is not implemented as a balanced tree
(\cf{bus-structure}), bus data will reach certain modules earlier than
others.  The {\sym Tree Balancing Delay} specifies how much closer the
given module is to the root than the farthest module in the tree.
Since modules that are closer to the root receive their commands
earlier (by one clock cycle per tree segment), a corresponding delay
is inserted by the \chip\ hardware before the start of a sweep
(\cf{RMR}) so as to allow all modules to sweep in lockstep.  Note that
this delay is not inserted during scan-io (\sect{SIOR}), and so no use
of glue should occur during this mode, since modules will not be
scanned in lockstep.

{\sym Test Mode Select} is used to put the \chip\ into special test
modes.  Each of the 16 {\sym TMS} values selects not only a test mode,
but also a single output value that can be made available through
{\sym Multipurpose Pin}s (\cf{MPCR}).  The choices are \memo{is this
table final?}
 \begin{equation}\label{eq.testmode}
 \begin{tabular}{|c|p{.75in}|p{1.25in}|}\hline
	\sym TMS & \multicolumn{1}{c|}{test mode} &
\multicolumn{1}{c|}{signal name}\\\hline
	0 & none & \\
	1 & none & \sym End Of Stretch Pulse \\
	2 & none & \sym End Of Sweep Pulse \\
	3 & none & \sym End Of Scan Pulse \\
	4 & & \\
	5 & & \\
	6 & & \\
	7 & & \\
	8 & & \\
	9 & & \\
	10 & & \\
	11 & & \\
	12 & & \\
	13 & & \\
	14 & & \\
	15 & & \\\hline
 \end{tabular}
 \end{equation}

A value of 1 for the {\sym Node Bypass Flag} indicates that \bus{}
signals and data entering the node on this chip from the inner (host)
side should be used directly by the \io\ circuitry, {\em without}
first passing through the node.  A value of 0 for this flag indicates
that these bus signals are first reclocked by the node, and only then
used (by the rest of the chip) {\em after} passing through the node.
Use of this flag (provided bus timing constraints allow it) makes it
easier to construct a balanced version of the \bus.

The {\sym Select Read Enable} bit is used when register 0, the {\sym
Module Select Register}, is read.  On such a read, the current
selection state of the \chip\ is ignored, and only \chip{}s that have
the {\sym Select Read Enable} bit set will respond (see \sect{MSR}).

According to its value, 0 or 1, the {\sym Active LUT Select} bit tells
which of the two \lut{}s (0 or 1) is currently active (cf.\ {\sym
Active LUT Toggle} in the {\sym Run Mode Register}, \sect{RMR}).
Writing this bit forces a specific \lut\ to become the active one.


\section{Multipurpose Pin Control Register}\label{sect.MPCR}

 \begin{register}{\ 10}{MPCR}{Multipurpose Pin Control Register}
	\compositeof
	\subreg{5}{MAFS}{Multipurpose A Function Select}
	\subreg{5}{MBFS}{Multipurpose B Function Select}
 \end{register}%
	The {\sym Multipurpose} pins (\sect{misc-pins}) are used for
input or output signals that need appear only once per module rather
than once per \chip. Each chip of a set will handle two different
signals through its two {\sym Multipurpose} pins, as instructed by the
{\sym Multipurpose Pin Control Register}.  We provide two of these
pins per chip so that even a module with a small number of \chip{}s
will have enough multipurpose pins to provide all essential signals.
This is convenient for constructing low-budget \step{} machines, and
also for reducing the number of \chip{}s needed to perform a complete
simulation or test of a working system.

There are 32 choices for the function of each of the {\sym
Multipurpose Pin}s.  For simplicity, we have exactly the same choices
available on both pins: the first four choices use the pin for input,
the rest of the choices are outputs.  The four input choices are:
 \begin{equation}\label{eq.multi-input}
 \begin{tabular}{|c|p{1.75in}|}\hline
	\sym MFS & \multicolumn{1}{c|}{Signal}\\\hline
	0 & \sym External Input \\
	1 & \sym External Interrupt \\
	2 & \sym Scan Input \\
	3 & \sym Status Input \\\hline
 \end{tabular}
 \end{equation}

\noindent The {\sym External Input} allows an external signal to be
delayed or inverted and come out on the other {\sym Multipurpose Pin},
if it is suitably configured as an output; the {\sym External
Interrupt} allows external hardware connected to the module to signal
an interrupt (see {\sym IER}); the {\sym Scan Input} makes it possible
to check for intermodule scan-synchronization errors (see {\sym IER});
and the {\sym Status Input} (coming from a module farther out on the
bus tree) is combined with the internally generated status signal to
produce the {\sym Status} output (see below).

\medskip

The rest of the {\sym Multipurpose Function Select} values indicate
that the corresponding {\sym Multipurpose Pin} is configured as an
output.  Each \chip\ generates all of the module signals that might be
needed; which signal is ouput to the pin is established by the {\sym
Multipurpose Function Select} according to the following table.

 \begin{equation}\label{eq.multi-output}
 \begin{tabular}{|c|p{1.75in}|}\hline
	\sym MFS & \multicolumn{1}{c|}{Signal}\\\hline
	 4 & \sym Status (Int/Scan) \\	
	 5 & \sym Node LSOUT \\
	 6 & \sym Node IOSEL \\
	 7 & \sym Node RSOUT \\
	 8 & \sym Box Data Enable \\	% was Display Active
	 9 & \sym SYNC (delayed) \\
	10 & \sym Node Data Direction \\
	11 & \sym Node Data Enable \\
	12 & \sym Scan Is Active \\
	13 & \sym Latch Glue Direction \\
	14 & \sym LUT0 Chip Select \\
	15 & \sym LUT0 Write Enable \\
	16 & \sym LUT1 Chip Select \\
	17 & \sym LUT1 Write Enable \\
	18 & \sym Site Output Data Valid \\
	19 & \sym Unglued Data Bit \\ 
	20 & \sym Host Supplied Bit \\
	21 & \sym SABSR Selected Bit \\
	22 & \sym Display Output Data Valid \\
	23 & \sym Run Type \\		% was Active LUT Output
	24 & \sym Active LUT Select \\	% was CAM Interrupt
	25 & \sym Active LUT Output \\	% was Scan In Progress
	26 & \sym CAM Interrupt \\	% was External Inverted
	27 & \sym Scan In Progress \\	% was External Delayed
	28 & \sym External Input Inverted \\	% was Box Enable
	29 & \sym External Input Delayed \\	% was Test Output
	30 & \sym Constant of 0 \\
	31 & \sym Constant of 1 \\\hline
 \end{tabular}
 \end{equation}

\noindent Choices 4--11 are \bus\ signals that are needed only once
per module; they are documented in \sect{bus}.  {\sym Scan Is Active}
(choice 12) can be used in conjunction with {\sym Scan Input} (choice
2) from another module to test that periods of active scanning occur
at the same time in both modules (for this test, the scan is {\em not}
considered to be active during {\sym Scan I/O}, \cf{SIOR}).  {\sym
Latch Glue Direction} (choice 13) is a pulse (intended for use by
external glue signal buffers) that occurs just before active scanning
begins; at this time, glue lines are either pulled up to indicate
inputs, or actively driven low to indicate outputs.  Choices 14--17
control the SRAMs that constitute the two LUTs in a module.  {\sym
Data Valid} (choice 18) is used in conjunction with choices 19--21,
and also the {\sym LUT Address} and the {\sym Flywheel Output} to mark
valid data bits.  {\sym Display Valid} (choice 22) has a slightly
later timing, and is used to indicate when the {\sym Display Output}
has valid data.  This timing is the same as that of the active LUT's
outputs, and the Flywheel input (except when used as an input to LUT
and FLY).  {\sym Run Type} (choice 23) reflects the value of the third
bit of the {\sym Run Mode Register}; it is used in conjunction with
choice 22 to indicate valid display output that occurs during a run of
a particular type -- for example, one that is meant to be sampled by a
frame buffer.  Similarly, {\sym Active LUT Select} (choice 24)
reflects the value of the last bit of the {\sym Hardware Environment
Register}, which indicates which of the two available LUTs is
currently active for updating.  {\sym Active LUT Output} (choice 25)
is a reclocked version of the actual output bit from the currently
active LUT.  {\sym CAM Interrupt} and {\sym Scan Requested} (choices
26 and 27) repeat the same information encoded in the {\sym Status}
signal (choice 4), but as two separate signals.  {\sym External Input
Inverted} (choice 28) reflects the value (inverted) of an {\sym
External Input} (choice 0) if such an input was selected at the other
{\sym Multipurpose Pin} of this \chip; similarly, {\sym External Input
Delayed} (choice 29) reflects an {\sym External Input} that has been
clocked through a single delay element.The {\sym Test MUX Output}
(choice 29) is an output that is determined by the current test mode
(see {\sym Test Mode Select} in \sect{HER}).  Finally, constants of 0
and 1 can be selected as choices 30 and 31 respectively.

\medskip

At reset time, the {\sym Multipurpose} pins are always configured as
inputs (choice 0), and the {\sym Module ID Register} is set from {\sym
Multipurpose Pin A}. This is used to distinguish one \step{} module from
all of the others in a given box (\sect{corner-box}), using pullups
and pulldowns.  After reset, in an unbalanced tree, all boxes except
the one at the root (corner) of the tree are cut off from the \bus\
until the root's {\sym Multipurpose Pin}s are configured.\footnote
	{The point in a \bus\ frame at which the new value of the
{\sym Multipurpose Pin} selections become enabled is chosen to make
enabling the \bus\ work properly.}
	This distinguishes the root box from all other boxes, and is
useful in establishing a distinguished module to use as the origin for
numbering the rest (i.e., the distinguished module in the corner box).


\section{Glue Pin Connectivity Register}\label{sect.GPCR}

 \begin{register}{\ 18}{GPCR}{Glue Pin Connectivity Register}
	\compositeof
	\subreg{3}{XMPC}{XM-Pin Connect}
	\subreg{3}{XPPC}{XP-Pin Connect}
	\subreg{3}{YMPC}{YM-Pin Connect}
	\subreg{3}{YPPC}{YP-Pin Connect}
	\subreg{3}{ZMPC}{ZM-Pin Connect}
	\subreg{3}{ZPPC}{ZP-Pin Connect}
 \end{register}%
	The {\sym Glue Pin Connectivity Register} is written at
setup time in order to determine what logical interconnection
should be associated with the physical interconnection provided by
each of the six glue pins (\sect{glue-pins}).

One use of this configuration flexibility is described in
\sect{block-improved}.  More drastic reconfigurations are possible.
Normally the glue pins define a three-dimensional array of modules,
interconnected as described in \chapt{block-structure}.  However, by
appropriately arranging the connectivity between modules, one can
connect them as a two-dimensional array (physically folded
back-and-forth over itself, with the folds piling up in the third
dimension), or even as a one-dimensional chain (\sect{}).

\medskip

\memo{make sure the terminology agrees}
 Each of the six connectivity registers corresponds to a {\em
physical} glue port (\chip\ pins {\sym XM}, {\sym XP}, {\sym YM},
{\sym YP}, {\sym ZM}, {\sym ZP}) and associates with it a {\em
logical} glue port ($x_-$, $x_+$, $y_-$, $y_+$, $z_-$, $z_+$, as
explained in \sect{}) or one of the constants 0 and 1.

Whenever the kick sign for dimension $x$ is positive, thus indicating
that logical port $x_+$ should be an {\em output} (\cf{}), then
any physical port that has been associated with $x_+$ by the {\sym
Glue Pin Connectivity Register} will be configured as an output and will
display the value of $x_+$; if more than one physical port is
associated with the same logical port, they will all behave alike.

When the kick sign is negative, thus indicating that logical port
$x_+$ should be an {\em input}, then any physical port associated with
$x_+$ will be configured as an input and will contribute a source of
data for $x_+$: if more than one physical port is associated with
$x_+$, their values will be {\sc or}ed before being passed on to
$x_+$.

Finally, if a physical port is associated with a constant, then it
will always be an output and display that constant.  The constants are
used during initialization for determining the physical connectivity
of the machine and initializing each module's ID (\sect{id-init}).

\medskip

\memo{Read and understand; maybe add a diagram} The value of {\sym
XM-Pin Connect} determines the logical glue ports (or the constant)
associated with the corresponding to physical port {\sym XM} according
to the following table (and similarly for the other five ports)
 \begin{equation}\label{eq.connectivity-choices}
 \begin{tabular}{|cc|c|}\hline
	\multicolumn{2}{|c|}{\sym XMPC}&\multicolumn{1}{|c|}{logical port}\\
	octal & binary &\multicolumn{1}{|c|}{or constant}\\\hline\hline
	0 & 00 0 & $x_-$\\
	1 & 00 1 & $x_+$\\
	2 & 01 0 & $y_-$\\
	3 & 01 1 & $y_+$\\
	4 & 10 0 & $z_-$\\
	5 & 10 1 & $z_+$\\\hline
	6 & 11 0 & 0\\
	7 & 11 1 & 1\\\hline
 \end{tabular}\
 \end{equation}

Each glue pin is internally pulled up by a resistor to a logical 1, so
that, when configured as an input and not otherwise driven, it will
sense a logical 1; this feature is used during module ID initialization
(\sect{id-init}).

Any glue pin which is not configured as a constant will act as an input
whenever the scan is not active.


\section{Module ID Register}\label{sect.MIDR}

\catcode`\@=11
\immediate\write\@auxout{\string
	\newlabel{sample-section}{{\arabic{section}}{\thepage}}}
\catcode`\@=12

 \begin{register}{\ \ 1}{MIDR}{Module ID Register}
 \end{register}%
	Each \step{} module has a unique {\em module ID}, which is
primarily used for module selection (\sect{modselect}); this ID is
assigned during hardware initialization (\sect{id-init}).  Each of the
16 \chip{}s of a set holds one bit of the module ID, in the {\sym
Module ID Register} ({\sym MIDR}).

At reset, the {\sym MIDR} is set to the value of the {\sym Multipurpose 
Pin A} (see \sect{id-init} for details).


\section{Group ID Register}\label{sect.GIDR}

 \begin{register}{\ \ 1}{GIDR}{Group ID Register}
 \end{register}%
	Besides the module ID, which is unique for each chip
(\sect{MIDR}), each \step{} module has also a {\em group ID},
which is primarily used for module selection (see \sect{modselect})
when one wants to address a whole group of modules rather than a
single one (see \sect{modselect}). Each of the 16 \chip{}s of a set
holds one bit of the group ID, in the {\sym Group ID Register} ({\sym
GIDR}).

Note that by using the {\em don't care} selection code (see table
\eq{selection-codes.rpt}) in some positions of the {\sym Module Select
Register} (\sect{SR}), one can select different groups
of modules based on data contained in different portions of the {\sym
GIDR}.


\section{Interrupt Enable Register}\label{sect.IER}

 \begin{register}{\ \ 10}{IER}{Interrupt Enable Register}
	\compositeof
	\subreg{1}{BPIE}{Bus Parity Interrupt Enable}
	\subreg{1}{BCIE}{Bus Contention Interrupt Enable}
	\subreg{1}{GCIE}{Glue Contention Interrupt Enable}
	\subreg{1}{MAIE}{Multi-A Contention Interrupt Enable}
	\subreg{1}{MBIE}{Multi-B Contention Interrupt Enable}
	\subreg{1}{SSIE}{Skewed Scan Interrupt Enable}
	\subreg{1}{XHIE}{External Hardware Interrupt Enable}
	\subreg{1}{RLIE}{Register Length Interrupt Enable}
	\subreg{1}{URIE}{Unknown Register Interrupt Enable}
	\subreg{1}{ISIE}{Invalid SYNC Interrupt Enable}
 \end{register}%
	The {\sym Interrupt Enable Register} is a collection of bits
that individually enable the interrupts described in the following
section, devoted to the {\sym Interrupt Flags Register}. An interrupt
will be recognized only if the corresponding {\sym IER} bit is set.
Since these interrupts all signal error conditions, their enables
should normally all be on.  Even in chips which don't have External
Hardware or Scan Input attached, the corresponding interrupts should
not signal an error, and so can be left enabled.

\medskip

An additional interrupt enable flag, associated with the verify-write
mode, is discussed in \sect{VWR}.

\section{Interrupt Flags Register}\label{sect.IFR}

 \begin{register}{\ \ 10}{IFR}{Interrupt Flags Register}
	\compositeof
	\subreg{1}{BPIF}{Bus Parity Interrupt Flag}
	\subreg{1}{BCIF}{Bus Contention Interrupt Flag}
	\subreg{1}{GCIF}{Glue Contention Interrupt Flag}
	\subreg{1}{MAIF}{Multi-A Contention Interrupt Flag}
	\subreg{1}{MBIF}{Multi-B Contention Interrupt Flag}
	\subreg{1}{SSIF}{Skewed Scan Interrupt Flag}
	\subreg{1}{XHIF}{External Hardware Interrupt Flag}
	\subreg{1}{RLIF}{Register Length Interrupt Flag}
	\subreg{1}{URIF}{Unknown Register Interrupt Flag}
	\subreg{1}{ISIF}{Invalid SYNC Interrupt Flag}
 \end{register}%
	The {\sym Interrupt Flags Register} is a collection of one bit
flags, each of which is set when the corresponding error condition is
detected (see \sect{cbus-interrupts} for details).

When an interrupt condition is detected by the \chip\ hardware, if the
corresponding enable flag is set (\sect{IER}) an interrupt will be
sent via the \bus\ to the \step{} interface, which in turn will
interrupt the host. Once the interrupt reaches the interface, further
interface operation is suspended until the host restarts it.

An additional interrupt flag, associated with the verify-write
mode, is discussed in \sect{VWR}.

\medskip

The contention interrupts indicate that a signal sampled at the output
of a bussed or bidirectional pin did not agree with the value that was
being driven.

A {\sym Bus Parity} error is indicated if the last completed \bus\ 
transaction didn't have overall odd parity, including the final Parity
bit that was sent.

A {\sym Skewed Scan} interrupt is signalled if the {\sym Scan Input}
is used, and disagrees with the internally generated {\sym Scan is
Active} signal.

An {\sym External Hardware Interrupt} is signalled if the {\sym
External Interrupt Input} is used, and it goes low.

A {\sym Register Length Interrupt} is signalled if a Register is
written by the host with an incorrect length, or if a register is read
by the host with too short a length.

An {\sym Unkown Register Interrupt} occurs if an attempt is made by
the host to access registers 29, 30, or 31.

An {\sym Invalid SYNC Interrupt} is signalled when one of the 4-bit
packets of video-SYNC timing information (see \sect{RMR}) coming in on
the SYNC input of the \chip\ (\cf{}) fails to have even parity.

\medskip

Note: the {\sym Interrupt Flags Register} is not cleared by a soft
(interface-initiated) \chip-reset.  This is done to facilitate error
recovery (see {\sym OSR} and {\sym DOCR}).


\section{Verify Write Register}\label{sect.VWR}

 \begin{register}{\ \ 3}{VWR}{Verify Write Register}
	\compositeof
	\subreg{1}{VWE}{Verify Write Enable}
	\subreg{1}{VWIE}{Verify Write Interrupt Enable}
	\subreg{1}{VWIF}{Verify Write Interrupt Flag}
 \end{register}%
	With an ordinary write frame, the transmitted data overwrite
the contents of the addressed register (or the contents of the
addressed \dram\ or \sram\ area, if the register is an I/O register).
The {\sym Verify Write Register} allows one to control a special {\em
verify-write} mode, where the transmitted data are simply compared
with this contents without changing it. This mode is enabled by
turning on the {\sym Verify Write Enable}.  Verify write is always
disabled while writing to the {\sym VWE} register itself, to make it
possible to turn the mode on and off.

In verify-write mode, an interrupt condition is signaled---by setting
the {\sym Verify Write Interrupt Flag}---if data written to a register
disagree with its contents.  Verify-write errors are only
signaled at the {\em end} of a data transfer (see the discussion of
data transfer errors in \sect{cbus-interrupts}).

Setting the {\sym Verify Write Interrupt Enable} allows the interrupt
condition to generate an actual interrupt. Enabling the verify-write
mode on a given \chip\ without enabling the corresponding interrupt
provides a way of {\em disabling} the writing of data on that chip.
In this way, one can ``write-protect'' one or more of the sixteen
layers, to change registers on some chips in the module and not on
others.  Note that this {\em write-per-bit} technique cannot be used
with the \lut{}s.


\section{DRAM Ones Count Register}

 \begin{register}{\ 16}{DOCR}{DRAM Ones Count Register}
	\compositeof
	\subreg{8}{LDOC}{Low DRAM Ones Count}
	\subreg{8}{HDOC}{High DRAM Ones Count}
 \end{register}%
	A \dram\ {\em ones counter} is an up/down counter that is
cleared, together with the \dram, at initialization time.  From then
on, each time a 0 in the \dram\ is changed to a 1, the counter is
incremented; each time 1 goes to 0, decremented; otherwise, it remains
unchanged.  Thus the counter should always reflect the number of ones
in the \dram\ (modulo the counter's size).

By using the event counter to occasionally count all locations in the
\dram, and comparing this count with that recoreded by the ones
counter, it should be possible to detect (with a high probability)
soft errors in the \dram.

\medskip

Each \chip\ has one \dram\ chip attached to it. The {\sym DRAM Ones
Count Register} consists of two independent {\sym DRAM Ones Count}s
({\sym LDOC} and {\sym HDOC}) that are associated repectively with the
low and high halves of this \dram.

By having separate counts for the two halves of the \dram, it becomes
possible to effectively handle errors on a large machine.  We split
the machine into two halves, each employing half of each \dram\ chip,
and both performing the same computation.  In the case of a miscompare
between the operation of the two halves, the {\sym DRAM Ones Count}s
make it likely that we can resolve which of the two halves got an
error, and then correct the errorneous data from the other half.

\medskip

The {\sym DRAM Ones Count Register} is not cleared by a soft
(interface-initiated) \chip-reset.  This is done to facilitate error
recovery (cf.\ {\sym OSR} (\sect{OSR}) and {\sym IR} (\sect{IR})).

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