\chapter{The Input-Output Section of the CAM-8 Controller Chip}

     This chapter describes the top level design of the input-output section 
of the CAM-8 controller chip.  The I/O section of the chip is responsible
for allowing the host to initialize and update the control registers, lookup
tables and system state.  It
also allows the host to read any status information that has been accumulated
in the module as a result of an experimental run. 

     A top-level block diagram of the I/O circuitry is shown in Figure~\ref{chipblk}.  In the following sections, the function and interconnection of
each block of the figure will be explained.

\begin{figure*}
\psfig{figure=chipblk.ps,width=6in}
\caption{Block Diagram of the I/O Section of the CAM-8 controller chip.}
\label{chipblk}
\end{figure*}

\section{The Register Bank}

     The Register Bank consists of a series of 1-bit and 8-bit registers
which store the control and status information associated with each 
controller chip.
This is the set of registers which the host needs to access.  All registers
are shift registers with their inputs tied to the serial
I/O data line and their outputs connected to the same line through tri-state
buffers.  The Register Select block enables one of the registers in the
register bank for I/O access.

     In Read mode, the tri-state associated with the selected register is
turned on so that the data contained in the register may be serially 
transmitted out along the I/O data line.  In Write mode, this tri-state
is turned off\footnote{The tri-state may actually be turned on depending
on the implementation of the Write-Verify logic.} so that the host can drive the I/O data line with the
data that needs to be written to the selected register.

     The registers of the Register Bank are wired to other parts of the
chip so that they may control the logic of these other sections.

\section{The Register Select Block}

     The Register Select Block is responsible for enabling one of the
registers of the Register Bank for I/O access.  It takes a Data Register
enable signal from the Enable Logic block and a register number from the
Opcode counter circuitry.  If the enable line is active, the register
specified by the counter is enabled.  Thus the Register Select block
acts as a decoder for the registers in the bank.  However, it
is not realized simply as a giant decoder.  Such a design 
requires too many wires running to the register bank.  Instead, this
block takes the form of combinational logic ANDs located in the proximity
of the individual registers in the bank.  The inputs of these ANDs are
tapped off a bus consisting of the register number and the enable signal.


\section{The Test/Verify Block}

     The Test/Verify block contains circuitry that compares bits stored in a
selected register with incoming bits from the host.  This
allows the host to verify the data that it has written to the Register
Bank.  If there is any
discrepancy between written and transmitted data, then an interrupt line
is activated to indicate the error. 

     It is thought that it would be optimum to always compare data that
is being written with the previous data in the selected register.  The
interrupt line, however, may only be set when the
Write-Verify operation is actually being performed.


\section{The Opcode Register Circuitry}

     The Opcode Register circuitry consists of a 7-bit opcode shift
register, a 7-bit counter and some combinational logic that enables the
counter.  

     The register that the host wishes to select for an I/O operation
is written to the opcode register when the I/O Select line is low.
The Enable Logic block ensures that the opcode register is enabled in
this case.  The number of the selected register is then written with the
least significant bit sent last.  This form of transfer allows some registers
to be specified without writing all 7 bits into the opcode register.

When the I/O Select line goes from high to low, the opcode register is
cleared by the Enable Logic.  Register one may be specified by sending a
single `1' before bringing the I/O Select line high again.  At this point, the
counter is loaded with the opcode register data and the selected register
number is provided to the Register Select block.

     The Counter Logic is used to implement an auto-increment feature
for register selection.  If the selected register is in the 1-bit register
space, then the counter is incremented with the arrival of every valid bit
of data.  If an 8-bit register is selected, then the increment occurs after
the arrival of 8 valid bits.  This allows registers  to be selected in
a sequential manner for I/O operations.

     Some registers are defined to be non-auto incrementable.  The counter
logic will inhibit the auto-increment feature on these registers.


\section{The Enable Logic}

    The Enable Logic is responsible for decoding a global module enable
signal provided by the Global Module Enable block into an opcode or data
enable signal.  It also generates the signal to clear the opcode shift 
register and to load the opcode counter.

    The Enable Logic uses the I/O Select line to generate its control signals.
If there is a Global enable and the I/O Select line changes from high to low,
then the clear signal to the opcode shift register is generated.  Under the
same enable, if this signal changes from low to high, then the load counter
signal is activated.  A global module enable on an I/O select line that 
is low  enables the opcode shift register,
while this enable on a high I/O select line enables the
data registers.

\section{The Module Select Block}

    This block is responsible for indicating whether the given module is
in fact selected for I/O purposes.  It contains comparison logic to
determine whether the host selected module or group matches the ID or
group number associated with the module.  It may therefore access some of
the registers contained in the register bank.  

     The module select block also takes as input the broadcast line from the
host.  Once this line is high, all modules are selected for a write operation.
An individual module may be selected by initiating a broadcast and writing the
ID or group number to the ID or group select registers of all the modules.
When the broadcast line is brought low, the module(s) corresponding to the
selected ID or group will be selected by the comparison logic of the module
select block.

\section{The Global Module Enable Block}

     The Global Module Enable block generates a global module enable signal
if a module is selected and the I/O bus is providing or expecting data.
The enable signal merely means that the chip should be either sending or
receiving data in that clock cycle.

     Essentially, this block acts as the interface between the chip and 
the PBus.  It turns on the chip when the bus is ready to accept or send
data, and it turns off the chip when the bus is full or empty.


\section{The Module Status Block}

     The Module Status block is responsible for providing the Empty or Full status of
the chip to the PBus node adjacent to the controller chip.  Because of the nature of the I/O design, the
controller chip is normally always ready to accept or send data.  Thus,
by default, the chip status is defined to be neither empty nor full.
However, for such functions as the update of the DRAM chip, the I/O needs
to interact with the scan circuitry, which may not always be able to process
data in one clock cycle.  In these cases, the module status may be affected
by the operation of the scan circuitry.  This circuitry is therefore allowed to
set and clear the full and empty bits.

