\chapter{Implementation of the CAM-8 Input-Output System}

     The previous chapters of this thesis have dealt with the design of the
CAM-8 input-output system.  Several factors have prevented a direct 
implementation of the design from being realized at the present time.  In this chapter
we explain  the implementation status
of each part of the system, what problems have been encountered, and any tests and simulations which have been
completed. Future system level simulations are also discussed.

\section{The Input-Output Section of the CAM-8 Controller Chip}

     The input-output section of the controller chip described in Chapter 4
was schematically entered using the VLSI Technology ASIC design software.
Appendix A shows the schematics of the various blocks described in Chapter 4.
The circuitry was developed using the VLSI Technology 1.0$\mu$ CMOS gate array
library primitives.  Design entry of the input-output section of the controller
chip was completed long before circuitry for the other blocks of the chip
had been developed.  As a result, it was impossible to predict all of the
registers which would be required for the final design.
An eight register input-output block was therefore developed for testing
purposes.  

   Each sub-block of the controller chip I/O system was simulated
using the VLSI gate array simulator to ensure that it met the system
requirements.  Once this was completed, the blocks were wired up together
and the entire eight register test version of the input-output block of the
controller chip was simulated.  Test code and output for these simulations
are shown in Appendix B.  The results were encouraging.  The eight register
test version of the circuit appeared to meet the goals of its design.  When the
control signals to the input-output section of the chip were 
toggled as they would in the final chip, the registers of the test version
were correctly read and written.  In addition, timing analysis revealed that
the test version of the chip correctly operated at clocking rates above 25MHz,
as required for the CAM-8 system.

     It was hoped that the design of the controller chip would have been 
completed by December 1989.  However, by January 1990, only the preliminary
eight register test version of the I/O block described above had been
entered into the system.  Work on the remainder of the chip is only now
progressing.  It was therefore impossible to obtain a fabricated chip to
test at the time of writing.  It is hoped that the controller chip would
be fabricated in the coming months.  Only then can the I/O circuitry 
shown in the schematics of Appendix A be truly tested.

\section{The Pipelined Input-Output Bus}

    The pipelined input-output bus (PBus) described in Chapter 3 has not
been physically built.  However, both the controller chip and interface board
circuitry have been designed to be compatible with the PBus protocol.
The initial CAM-8 hardware will probably consist of only two CAM-8 space
modules.  The PBus for such a system will take the form of a series of 
connecting wires --- the depth of the bus will be zero.  Indeed, it will
probably be several years before a CAM-8 machine of sufficient size is 
developed to require a PBus with any real tree-like structure.  The physical
implementation of the PBus was therefore given low priority in the project.
This is not to say that the PBus protocol would not be tested.  Since 
PBus compatible circuitry has been built into the controller chip and 
interface board, even the initial CAM-8 machine will exercise the design
of the PBus protocol.  The circuitry contained in a PBus node is 
relatively straightforward, and should not present a major implementation
problem when it is required.

\section{The Interface Board}

     The design and implementation of the interface board proved to be
the most challenging part of the input-ouput system.  The problem involved
interfacing the system to the high speed (20MHz) SBus of the Sun Sparcstation.
Economic and practical considerations dictated that the interface board
be implemented with some combination of programmable logic devices.  After all,
only one interface board is needed for a CAM-8 machine of any size.  Also, 
especially in the initial phase of development, it was advantageous
to have an implementation which could easily be modified should the need arise.

   Most of the programmable logic devices, however, proved to be too slow in
their implementation of the complex logic required by the SFSM of the interface
board.  Initially, the SFSM was designed as a single eight state machine.  This
machine appeared to be logically correct and efficient.  Boolean equations for
the eight state SFSM were entered using the Xilinx Programmable Gate Array
logic entry system.  The design was compiled, optimized, placed and routed on
the fastest Xilinx 3090 programmable gate array available.\footnote{The
100MHz toggle rate chip was used.}  Timing analysis of the routed chip indicated
that even without pad connections or the remaining system datapaths, the logic
could operate at best only at about 15MHz.  This was unacceptable for the 
interface board. 

     The SFSM was restructured in many ways in attempts to speed up the circuit.
The architecture of the Xilinx 3090 programmable gate array was studied, and
the state realizations and equations were modified specifically for this
architecture.  Repeated attempts succeeded in reducing the worst case delays
by several nanoseconds at best.  The problem was the complexity of logic ---
which could only be reduced at the loss of interface board functionality.
Each level of logic in the Xilinx realization required a fixed delay time
through the chip.  Routing delays were also unpredictable and excessively
high, sometimes of the order of 15 to 25 nanoseconds.  After about a month
of frustrating trials, it was concluded that the Xilinx chip was inadequate
for the purposes of the interface board.

     Other programmable logic families were investigated.  Discussions were
held with representatives of Actel and Altera Corporations.  The Actel 
engineers were skeptical that a 20MHz SFSM could be implemented even with their
fastest chip.  During this period, plans were made to attempt to enter the
control circuitry for the interface board into a Mosis 2.0$\mu$ standard
cell, which could be fabricated in several weeks at a relatively low cost.
The SFSM and PFSM were entered into the VLSI standard cell system using the
VLSI tools state machine entry language.  Some simulation of the state machines
were done.  However, an extensive timing analysis was not completed.

     By this time, the Altera MAX programmable entry software was acquired on
a trial basis.  The SFSM controller was entered into the system using the
Altera Hardware Description Language (AHDL) and the design was compiled into
the Altera MAX5064 chip.  Simulation of the design using the MAX simulator
proved that the SFSM timing was only just met.  This was encouraging, but
still unsatisfactory, since datapath delays would need to be included in the
system timing.  The SFSM was restructured into its present implementation so that it
could be compiled into two smaller and faster Altera MAX5032 chips.  

     Simulation of this design on the MAX simulator was successful.  The
SFSM operating rate of 20MHz could be comfortably realized with the fastest
grade MAX5032-1 parts.   Test vectors were written to exercise the possible
situations with which the SFSM would be required to cope.  The SFSM seemed to
operate correctly in all of the test cases.  

    The PFSM was structured in a similar manner and compiled into a single
Altera MAX5032-1 chip.  Simulations of the PFSM under worst case conditions
proved that it could correctly operate at the required 25MHz CAM-8 clock
rate.  The AHDL text description files for the SFSM and PFSM are shown in
Appendix C.  Compiled pinouts for the Altera chips are in Appendix D and
test vectors and simulation output are shown in Appendix E. 

    The parity generation hardware was also targeted into an Altera 
MAX5032-1 chip.  It was compiled and tested using the MAX software.  Appendix
C shows the AHDL text file for this chip.  Simulation output for the
parity chip can be found in Appendix E.  The parity chip simulated
at the PBus clock rate and appeared to behave in the correct manner.
   
    The problems of the interface board implementation were not over, however.
Because the board uses SBus word transfers, 32-bit wide registers were required
for the Control, Datain, Dataout and slave registers.  A physical
realization of these registers presented a major problem.  Discrete logic 
components could be used, but they would require a large board area and
numerous interconnecting traces.  This would easily exceed the maximum 
SBus double width board area (6.6in by 5.58in) and capacitive loading
(20pF per signal).  A programmable logic implementation was tried.  However,
the large number of registers meant that the realization would require 
several programmable chips.  There was also the problem of driving the SBus
lines to meet the SBus setup time of 15ns.  At the present time, other 
alternatives for the interface board register banks are being investigated,
including possibly a specialized Mosis chip containing all of the registers.
The Mosis chip is a real possibility since it would be compact and there 
is a low
risk of failure since relatively simple logic would be used on the chip.

   It is thought that once the register bank problem is overcome, a prototype
of the interface board should be easy to produce --- the slave FSM and
remaining glue logic could be programmed into another Altera chip.  Several
Altera MAX5032-1 chips have been special ordered\footnote{These chips are
not presently available commercially.} and are expected soon.

     It is the author's belief that the many problems encountered in the
implementation of the interface board is a direct result of trying to use
a technology unsuited to the target device.  The interface board contains
logic that is almost as complicated as that of the CAM-8 controller chip
itself.  The stringent requirements which must be met by SBus expansion
devices only serve to complicate the practical realization of this logic.
According to {\em The SBus Specification}, the SBus is ``intended for use
as a chip-level interconnect between components.''  The specification also
states ``From an electrical and performance perspective, the setup, hold and
delay requirements of the bus are compatible with modern CMOS families, such
as FCT, and the current and upcoming generations of CMOS gate arrays (such
as LSI Logic 9K and 100K families).'' 

     Virtually every board in the
Sparcstation which interfaces to the SBus contains some sort of high performance
CMOS gate array controller which performs the interfacing.  Clearly the
CAM-8 interface board should really be implemented in a high performance gate 
array as well.  Such a realization will easily meet SBus card size, timing
and electrical requirements as dictated by {\em The SBus Specification}.
Unfortunately, the CAM-8 project has reserved gate array development for
the controller chips rather than the interface board.  This is quite
reasonable given the practical and economic considerations.  The author's
point is simply that there is a better and more efficient way to 
implement the CAM-8 interface board which could overcome many of the 
problems that have plagued the current realization.  It is hoped that once
the preliminary programmable interface board has been fully 
debugged and tested, its
logic can be integrated onto a gate array in later months.

\section{System Level Simulations}

    Once the design of the CAM-8 controller chip is completed, a thorough 
system level software simulation of the entire CAM-8 machine will be
conducted.  This simulation will be performed with the Verilog simulator.
A behavioral model of the SBus has already been acquired from Sun Microsystems 
for this simulation.  Behavioral models for the interface board, the PBus
and the controller chip are currently being developed. 

     Several simple CAM-8 experiments will be executed on the system level
simulator.  The performance of all of the CAM elements, including the 
input-output system, will be carefully monitored.  The Verilog simulations
should uncover any unforeseen bugs in the machine.  Necessary modifications
to the interface board or controller chip will be made before the chip is
fabricated.  Fabrication of the controller chip and final modifications to
the interface board hardware will take place only after the CAM-8 system
has performed satisfactorily under the Verilog simulations.



 
