\section{The Interface Board System}

     This section provides a system level overview of the interface board
hardware organization.
A top level block diagram of the board is shown in Figure ~\ref{board}.  For master
operation, 
two finite state controllers are utilized: an
SBus FSM (SFSM), which runs at the SBus clock rate; and a PBus FSM (PFSM),
which operates at the CAM-8 clock rate.  These controllers oversee the
loading and unloading of the Control, Datain and Dataout registers.
A Slave FSM which operates at the SBus clock rate controls the board in slave
mode.  This involves loading and driving the Slave Register Bank contents.
The interface board also contains a timeout counter and interrupt hardware.
These allow the board to interrupt the host should a timeout or error condition
be encountered.  A Parity Generator on the board produces serial odd parity
bits for data transfers over each of the 16 PBus data lines.

     To transfer data from the SBus to the PBus, the data must first be loaded
into the Control or Datain registers by the SFSM using the SBus protocol.
Subsequently, data is driven from the Datain registers onto the PBus by the
PFSM, which uses the PBus protocol.  A reverse data transfer uses the
Dataout registers to hold the data in transit.  These registers are loaded 
by the PFSM and driven by the SFSM.

    In the following subsections, the functionality of the different blocks 
shown in the system block diagram will be explained in further detail.

\begin{figure*}[t]
\begin{center}
\mbox{\psfig{figure=board.ps,width=6in}}
\end{center}
\caption{Block Diagram of the Interface Board.}
\label{board}
\end{figure*}

\subsection{The Control Registers}

     The Control Registers store the present Display List instruction word
that is being executed.  The instruction word parameters were described in 
detail in the previous section.  The
Control Registers are loaded by the SFSM in accordance with the SBus protocol.

 Both the SFSM and PFSM interpret the contents of the Control registers 
for processing
the data.  For example, the PFSM loads the transfer length from these registers in order to transfer the correct number of PBus words during a CAM read
or write.  It also obtains the contents of the Opcode register from the 
Control registers
before it starts a data transfer to CAM-8.  The SFSM uses the
Start Address of Transfer and Next Display Item pointers in the Control Register
word to further access memory for subsequent data and instruction transfers.
The SFSM also uses the conditional information of the Control Registers to
coordinate waits between Display List instructions.

     The contents of the Start Address or the Next Display pointer registers are driven on the
data lines of the SBus by the SFSM when the board initiates a data transfer
over the SBus.

\subsection{The Datain Registers}

    The Datain Registers consist of four 32-bit registers which are loaded
from the SBus by the SFSM.  These registers hold any data that is in transit
from the SBus to the PBus.  Once the Datain registers have been loaded with data, the PFSM is triggered
to transfer their contents over the PBus. Of course, 
during the PBus transfers, the Datain Registers are read as 16-bit CAM-8
data words. The registers may be reloaded with new data until the
entire DMA transfer to CAM-8 has ended.

\subsection{The Dataout Registers}

    The Dataout Registers consist of eight 16-bit registers.  They are 
loaded from the PBus by the PFSM and contain data that is in transit from the
PBus to the SBus.  Once the Dataout registers have been loaded, the SFSM is triggered to transfer their contents
over the SBus.  The registers are driven as four
32-bit registers on the SBus and may be reloaded with new data until the
entire DMA transfer from CAM-8 has ended.

\subsection{The SFSM}

   The SFSM is a finite state machine controller which is clocked at the
SBus clocking rate.  It interprets and executes the `program' that is stored in the
Display List.  This involves correctly loading the Datain Registers;
driving the Dataout Registers; and holding up program execution until
specified conditions are met.

\subsection{The PFSM}

   The PFSM is a finite state machine controller that is clocked at the
PBus or CAM-8 clocking rate.  When a new instruction is read into the
Control Registers, the PFSM generates the sequence of PBus control signals
to transfer the Opcode Register contents over the PBus.  For a write 
to CAM-8, the PFSM then proceeds to drive the contents of the Datain Registers
over the PBus.  For a read from CAM-8, it loads the Dataout Registers with
the requested data. 

   The PFSM is also responsible for decrementing a counter
that contains the remaining length of the data transfer.  When that value 
has been decremented to zero, the SFSM is informed that the data transfer
is complete. 

\subsection{The Slave Register Bank}

    The Slave Register Bank consists of three 32-bit registers and several
32-bit hardwired values.  The three registers are used to store the pointer to
the Next
Display List item supplied by the host, the address of the current 
instruction being executed, and the interrupt polling bits to be read by the
host.  These are required registers for the proper
operation of the interface system.  The remaining hardwired values are
those required by Sun for any SBus slave.  They include the board ID number
and other slave tokens.  The contents of any item in the Slave Register bank 
may be 
driven by the Slave FSM over the SBus.  The pointer to the Next Display List
item is loaded from the host, but the current instruction address is loaded
from the board by the SFSM.  This is explained in further detail in a later
section.  The interrupt polling bits are set by the Interrupt Hardware and
read by the SBus Controller.

\subsection{The Slave FSM}

    The Slave FSM operates at the SBus clock rate and coordinates the board
as an SBus slave.  It monitors the SBus control signals and generates correctly
timed load and drive pulses to the Slave Register Bank.  The Slave FSM operates
independent of the other two FSMs in the interface board system.

\subsection{The Timeout Counter}

    The timeout counter is an 8-bit counter which is used to generate an
interrupt to the Interrupt Hardware if there is no response from CAM-8 
within 256 clock cycles of a CAM read operation.

\subsection{The Interrupt Hardware}

    The Interrupt Hardware is responsible for activating an SBus interrupt
to request CPU intervention on the board.  Interrupts may be generated if
data transfer errors or timeouts occur, or if the Display List instruction 
word specifically requires the host to write to the Host Next Pointer 
register.

\subsection{The Parity Generator}

    The Parity Generator produces parity bits for PBus data transfers.
 Parity generation begins with the transmission of the first bit of
the Opcode register over the PBus and continues until the current data transfer
is complete.  A serial odd parity bit is generated for each of the 16 PBus data
lines.  The parity word is transmitted to CAM at the end of the current data
transfer.  This word is used by the controller chips of CAM-8 to determine
whether there were any transmission errors over the PBus. 
