\section{Datapath Specifications} 

    This section describes in detail the datapaths and hardware
organization of the interface board.  The Control, Datain and Dataout
register banks are discussed.  In addition, the necessary synchronization
circuitry, timeout counter, and interrupt and parity generation hardware for 
the board are presented in this section.

\subsection{The Register Banks}

     The Control, Datain and Dataout registers are arranged in banks
each consisting of four 32-bit registers.  Each bank is separately addressed by the SCTR and PCTR counters.  The SFSM accesses the register that is pointed to
by the SCTR while the PFSM accesses the register addressed by the PCTR.  Thus
all SFSM control signals to the register banks activate the register pointed to
by the SCTR, while all PFSM signals affect the PCTR addressed register.

\subsection{The Control Registers}

     The Control Registers logic diagram is shown in Figure ~\ref{ctlreg}.  These
registers store the four 32-bit SBus words which 
make up a single Display List instruction.  The Control Registers are labelled
R0 thru R3.  Their contents are as follows:

\noindent
\hspace*{2cm}
R0 : Flags, Condition Bits, Opcode Contents
\newline
\hspace*{2cm}
R1 : Start Address of Transfer or Immediate Data
\newline
\hspace*{2cm}
R2 : Length of Transfer in Half Words
\newline
\hspace*{2cm}
R3 : Pointer to Next Display Item
\newline
   Each of the four Control Registers will now be examined in greater detail.

\begin{figure*}
\psfig{figure=ctlreg.ps}
\caption{The Control Registers of the Interface Board.}
\label{ctlreg}
\end{figure*}

\subsubsection{The R0 Control Register}

   The high 16 bits of the R0 register contain flags such as WR;
the immediate flag, which says whether the data is immediate; as well as the
condition bit encoding which declares what condition, if any, the board should
wait on before executing the next Display List item.  The low 16 bits 
include the 7-bit Opcode contents which declares the CAM-8 register to which
the data transfer is directed.

    Both the SFSM and the PFSM read the information contained in R0.  A shift
register clocked by the PBus clock loads the Opcode contents from
R0 when LDCTL is active.  The shift register allows the PFSM to shift the
Opcode data to CAM-8 using the PBus
protocol.  Shifting is controlled by the PSH line of the PFSM. A `0' is always
 shifted into the shift register.  Thus,
when all the shift register bits are zero, no further shifting to CAM-8 is
needed for Opcode specification.  At this point, PSELDONE becomes active.
The serial output of the shift register is fanned out to the 16 PBus data lines
through tristate drivers.  These drivers are enabled when both PIOSEL and DRPTY
are low.
Thus, whenever this is the case, the PBus data lines are driven with the 
required Opcode data.

\subsubsection{The R1 Control Register}

    The contents of the R1 register depends on the value contained in the 
Immediate flag bit of R0.  If this flag is active, then R1 contains the value
of the immediate data to be sent to CAM-8.  This data would have been loaded into
the first Datain Register at the same time that R1 was loaded.

     When the immediate flag is not active, R1 contains the starting virtual
address of the DMA transfer.  In the case of a write to CAM-8, this is the
address of the first 32-bit word to be sent as data to the selected CAM-8 
register.  For a read from CAM-8, the address represents the start address to
which data from CAM-8 should be written.

     The R1 register also acts as a counter during DMA transfers.  Since all
transfers are 16 byte burst transfers, INCADR is asserted by the SFSM to increment the
virtual address by 16 bytes upon the completion of each successful burst.
This ensures that the correct address is driven onto the SBus for the subsequent
burst transfer.

\subsubsection{The R2 Control Register}

   This register contains the length in CAM-8 words (or SBus half-words) of the
data transfer.  The LDCTL signal loads the transfer length into a length counter clocked by
the PFSM.  This counter is decremented with each PBus word transfer.  When the
counter value becomes zero, the DONE flag is set to indicate that the transfer
is complete.  The flip-flop structure that is gated to generate DONE serves to
turn the DONE flag on or off.  This is useful to avoid interpreting the DONE
from a previous transfer as valid for the present transfer.  Essentially, the
PFSM sets the DONE lookout flag on by asserting LDCTL when it loads the length counter with new data.  The flag is taken off by the SFSM when a data transfer
has been completed.  This is achieved by the assertion of CLRDONE.

\subsubsection{The R3 Control Register}

   The R3 Control register contains the pointer to the next item of the 
Display List.  When the current instruction has been executed, the contents of this register is driven onto the
SBus as the virtual address of the next intruction of the Display List to be
executed.  There is one exception, however.   If there is a Wait-for-Host
condition and the HOSTFLG has been set, then the next instruction pointer is
driven from the slave Host Next Pointer register.  In this case, the drive
line to R3 is inhibited.

    Strictly speaking, if there is no required branching in the Display List
execution, this portion of the Display List word would not be needed.  The 
program counter could simply be incremented as each instruction is executed.

    The loading of R3 sets the instruction ready (SR3DAV)
flag.  This informs the PFSM that a valid instruction has been loaded into
the Control Registers.  The PFSM acknowledges this by clearing the flag with
LDCTL when it loads the instruction data into the shift register and length
counter.

\subsection{The Datain Registers}

     The Datain Registers logic diagram is shown in Figure ~\ref{datain}.  These registers
 are loaded as four 32-bit registers
from the SBus and driven as 16-bit registers onto the PBus.  As in the case 
of the Control Registers, the SCTR and PCTR counters select the register to which
load or drive signals are applied.

     The loading of each 32-bit Datain Register from the SBus sets a data available flag
(labelled SR4DAV thru SR7DAV).  These flags inform the PFSM that valid data is
present in the registers.  Thus the PFSM may begin transferring data from R4 to 
CAM-8 even before register R7 is loaded.  This reduces the transfer time
for data to be written to CAM-8.  The data available flags are
reset by the PFSM with the assertion of PCWR.

     When the PFSM has driven the last CAM-8 data word onto the PBus,\footnote{
This will occur when the last half-word of R7 is driven.} the PDRW flag
is set.  This informs the SFSM that all data written to the Datain registers
have been processed.  These registers may now be refilled with new data.

\begin{figure*}
\psfig{figure=datain.ps}
\caption{The Datain Registers of the Interface Board.}
\label{datain}
\end{figure*}

\begin{figure*}
\psfig{figure=dataout.ps}
\caption{The Dataout Registers of the Interface Board.}
\label{dataout}
\end{figure*}

\subsection{The Dataout Registers}

     The Dataout Registers are shown in Figure ~\ref{dataout}.  Their setup is very similar
to that of the Datain Registers described above.  Here, however, each register
is loaded as two 16-bit registers from the PBus and driven as a 32-bit register
onto the SBus.  The Dataout Registers are clocked at the CAM-8 rate.

     During a read from CAM-8, the Dataout Registers are loaded with data from
the PBus as quickly as possible.  Once the final half-word of R7\_OUT is 
loaded, the buffer becomes full and the PDRD flag is set.  This stimulates the
SFSM to drive the contents of the registers onto the SBus.  When the SBus 
transfer is complete, the SFSM clears the flag by asserting SCRD.  The PFSM
may now refill the registers with new PBus data.

     The OR gate that logically ORs the PDRD and DONE signals requires some
explanation.  If the number of CAM-8 words to be read is not a multiple of
eight, then the Length counter would be decremented to zero before the 
Dataout buffer is full.  Once the length has gone to zero, however, the SBus
transfer should be started since all required data has been read from CAM-8.
Thus the data available flag to the SFSM is the logic OR of DONE and PDRD.
Note that it does not matter that data is always transmitted in groups of eight CAM-8
words.  The host which processes the data read from CAM-8 should
just read the correct number of words that it expects from the transfer.  The
contents of the remaining words are meaningless to the host in this context. 
     


\subsection{Synchronization Hardware}

     The interface board contains two completely asynchronous clocked 
 subsystems --- the SBus clocked SFSM and the PBus clocked PFSM.  Status 
bits from one system to the other must be correctly synchronized to the
clock of the controller to which they are input.  The synchronization is
illustrated in Figures ~\ref{davsync} and ~\ref{gensync}. 

\begin{figure*}
\psfig{figure=davsync.ps}
\caption{Synchronization of the PDAV signal.}
\label{davsync}
\end{figure*}

\begin{figure*}
\begin{center}
\mbox{\psfig{figure=gensync.ps}}
\end{center}
\caption{Synchronization of SFSM input signals.}
\label{gensync}
\end{figure*}

     The data available bits from the SFSM to the PFSM are multiplexed to
generate a single S-synchronized data available line.  This line passes 
through an S-to-P synchronizer which synchronizes it to the PFSM.  The output
of the synchronizer is the PDAV signal.  As shown in Figure ~\ref{davsync}, the PCTR 
determines which of the SRDAV lines is to be interpreted as the PDAV signal
at any given time.

     Figure ~\ref{gensync} shows that the PDRD1, PDRW and PFSM generated DONE signals are
synchronized to the SFSM to generate the DRD, DRW and DONE inputs respectively.
In addition, the selected condition bit is synchronized to the SBus clock
before it is input to the SFSM.

     The S-to-P and P-to-S synchronization are achieved by passing the signal
to be synchronized through two serially connected D-type flip-flops clocked
at the synchronizing clock rate.  The output of this arrangement is a 
correctly synchronized input signal.

\subsection{The Timeout Counter}

     The interface board contains an 8-bit Timeout
counter which is clocked at the PBus or
CAM-8 clocking rate.  It serves to interrupt the host if there is no
response from CAM-8 within the first 256 clock cycles of a CAM read.
This would indicate that an invalid module select ID had been written to
CAM, or that there is some malfunction in the CAM-8 hardware.  In either
case, an interrupt line must be generated to the host so that the situation
can be further investigated.

\begin{figure*}[t]
\begin{center}
\mbox{\psfig{figure=timeout.ps,width=6in}}
\end{center}
\caption{The Timeout Counter of the Interface Board.}
\label{timeout}
\end{figure*}

     As shown in Figure~\ref{timeout}, the Timeout counter is cleared
by the LDCTL line from the PFSM.  Counting is enabled if EOFIN is high
and  the PBUSDIR line
is low --- that is, during a CAM read.  If the EOFIN line becomes low
before the timeout, then CAM has responded to the read request, and
the counter is disabled.  The ripple carry out of the counter is deglitched
through a flip-flop to produce the TIMEOUT signal to the Interrupt Hardware.

\begin{figure*}[t]
\begin{center}
\mbox{\psfig{figure=interrupt.ps,width=6in}}
\end{center}
\caption{The Interrupt Hardware of the Interface Board.}
\label{interrupt}
\end{figure*}


\subsection{The Interrupt Hardware}

     Figure~\ref{interrupt} shows the realization of the Interrupt Hardware
of the interface board.  This circuitry is responsible for triggering an
interrupt to the host CPU if a timeout, error condition, or programmed 
interrupt is encountered.

    As mentioned above, a Timeout interrupt is generated if a CAM read is requested and CAM
does not respond with data within 256 CAM clock cycles.  An Error interrupt
is generated by the SFSM if either an Error Acknowledgment or Late Error is
encountered during an SBus transaction.  
 A ``soft'' interrupt is a programmed interrupt to the host.  It is initiated
if the Interrupt bit in the Flag field of the instruction word has been set.
 The ``soft'' interrupt is primarily used to stimulate the host to
write a new Host Next Pointer to the interface board.

    As shown in Figure~\ref{interrupt}, if an interrupt condition occurs,
the SBus {\sf IntReq(7)*} line is pulled low.  At the same time, SPOLREG is
generated to set the polling register of the Slave Register Bank.  The
{\sf IntReq(7)*} line is kept asserted until the host reads the polling 
register.  At that time, the interrupt line to the host is unasserted.

\begin{figure*}
\psfig{figure=edgefsm.ps}
\caption{The Edge Detection FSM of the Parity Generation Hardware.}
\label{edgefsm}
\end{figure*}

\subsection{The Parity Generation Hardware}

    The Parity Generation hardware of the interface board is implemented in
state machines programmed into an Altera MAX5032 chip.  An edge detection 
FSM is used to ascertain when the PBus I/O Select line transitions from high
to low. In accordance with the PBus protocol, the parity word should be
transmitted at that time. Sixteen parity bit generation machines produce the 
serial parity bits which are transmitted over the PBus.

    Figure~\ref{edgefsm} shows the bubble diagram for the edge detection FSM.
Upon reset, the system enters the LOW state.  It remains in this state until
PIOSEL goes high.  At that time, there is a transition to the HIGH state.
The edge detection FSM remains in HIGH until PIOSEL goes low, when there is
a transition to the TRANS state.  In the TRANS state, the tri-state drivers
on the parity generation chip are enabled by DRPTY so the current parity word is driven
on the PBus.  The system remains in TRANS until
both EOFIN and EOFOUT are asserted.  This indicates that the PBus is sampling
the parity word.  On the following clock cycle, there is a transition back
to the LOW state.

   The parity generation FSM is shown in Figure~\ref{ptyfsm}.  This two state
machine is replicated 16 times in the parity generation chip.  A parity
generation FSM is associated with each of the 16 PBus data lines.   Upon reset,
or one clock cycle after the successful transmission of the last parity word
over the PBus (DRPTY\_Q), the parity generation FSM goes to the default PAR1 
state.
In this state, the parity bit (PARBIT) is 1.  The PBus data line is monitored
for data transmissions.  If there is a successful non-parity transmission
over the PBus (/EOFIN*/(EOFOUT+DRPTY)) and a logic 1 is transmitted, there
is a transition to the PAR0 state where the PARBIT is 0.  The system stays in
PAR0 until a logic 1 is successfully transmitted as data over the PBus.  There
is then a transition back to the PAR1 state.  This procedure continues until
the CAM data transfer is complete.  The current state of the parity generation
machines is then transmitted as the parity word, and all of the machines
are automatically reset to the PAR1 state.

     Figure~\ref{iotim} is a timing diagram for a typical write over the PBus.
The PBus is always enabled in this example (EOFIN is never high).  The Opcode,
Dataout and parity tristate drivers of the PBus are never turned on in the
same clock cycle that another driver is turning off.  This eliminates contention
in the system.

\begin{figure*}
\psfig{figure=ptyfsm.ps}
\caption{The Parity Generation FSM.}
\label{ptyfsm}
\end{figure*}


\begin{figure*}
\begin{center}
\mbox{\psfig{figure=iotim.ps,width=6.0in}}
\end{center}
\caption{Time Line Diagram for a typical PBus write.}
\label{iotim}
\end{figure*}


