\section{The PFSM of the CAM-8 Interface Board}

    This section describes the PFSM that is used on the 
interface 
board.  The PFSM controller operates at the CAM-8 clocking rate and 
performs the following functions:

\begin{itemize}
    \item Writes the Opcode Register of CAM-8 with the correct value.
    \item Sequentially drives the contents of the Datain Registers to 
          CAM-8 over the PBus during a write to CAM.
    \item Sequentially loads the Dataout Registers from the PBus during
          a read from CAM.
    \item Decrements a length counter with each successful transfer over
          the PBus and sets a flag when the entire data transfer is complete.
    \item Handshakes with the SFSM for the most efficient operation of the
          board as a whole.
\end{itemize}

     As in the case of the SFSM, the functionality of the PFSM was distributed
over a few small finite state machine controllers.  State transition diagrams
of these FSMs are shown in Figures~\ref{pctlfsm}, ~\ref{pwrfsm}, ~\ref{prdfsm}
and ~\ref{pedgefsm}.  A PControl FSM detects 
the arrival of a new instruction word and shifts the Opcode data over the
PBus to CAM-8.  If a CAM write is required, the PWrite FSM then takes over and
transfers data from the Datain registers to CAM.  If a CAM read is to be
executed, a PRead FSM changes the PBus direction and then performs the transfer
from the PBus to the Dataout registers. A PEdge FSM synchronizes the operation
of the PFSM to that of the parity generation chip.  This allows the
PFSM to assert the EOFOUT line when the parity chip is ready to drive the
parity word onto the PBus.
The remainder of this section describes the operation of these finite state
machines in terms of their state transition bubble diagrams.

\subsection{The PControl FSM}

    The PControl FSM is shown in Figure~\ref{pctlfsm}.  This FSM is responsible for the initial phase of the execution 
of a data transfer.  All data transfers to or from CAM-8 are preceded by an
Opcode register write.  This specifies the CAM-8 register which is to be
accessed when the data transfer begins.  The PControl FSM loads the
Opcode value contained in the Control registers into a P-clocked shift 
register.  It then shifts this value over the PBus while correctly toggling
the I/O Select line as required by the PBus protocol.  

     The PControl FSM also loads the transfer length counter from the
Control registers into a PFSM controlled decrementable counter.  In addition,
it enables the DONE flag and resets the instruction ready flag.

\subsubsection{The PINIT State}

   Upon reset, the PControl FSM enters the PINIT state.  In this state, LD is
asserted and PC is set to 1.  This loads the value 011 into the PCTR on the
next clock edge.  This means that the PCTR selects the last Control register.
Thus a high on PDAV would indicate that an instruction has been loaded into
the Control registers by the SFSM.  The PBus direction is also set so that the
interface board can write to CAM-8.  There is an unconditional transfer from
the PINIT to the PIDLE state.

\begin{figure*}
\psfig{figure=pctlfsm.ps,width=6in}
\caption{The PControl FSM of the PFSM System.}
\label{pctlfsm}
\end{figure*}


\subsubsection{The PIDLE State}

    The PControl FSM waits in PIDLE until PDAV is asserted and the parity 
flag is clear.  This indicates 
that the previous parity word has been transmitted to CAM and a instruction has been loaded into the Control registers.  When this
occurs, the PCTR is loaded with the value 100 so that the first Datain or
Dataout register may be accessed by the other FSMs.  LDCTL is asserted to
load Opcode and transfer length data into P-controlled registers and to
clear the instruction ready (PDAV) flag, enable the DONE flag and clear the
Timeout counter.  There is then a transition to the OPSHIFT 
state.  

\subsubsection{The OPSHIFT State}

    In the OPSHIFT state, the contents of the CAM-8 Opcode register is shifted out
over the PBus. 
The system waits in OPSHIFT until DONE becomes asserted, EOFIN goes low or PSELDONE goes high.
A low on EOFIN indicates 
that the PBus can accept valid data.  
While EOFIN is low and PSELDONE is unasserted, the 
contents of the Opcode register is shifted over the PBus by the assertion
of PSH and EOFOUT.  Once PSELDONE goes high, the shifting is complete,
and the OK flag is set to initiate the other system FSMs.  The PIOSEL line
is set high by SIOSEL for the subsequent transmission of data over the PBus.  The PControl FSM
 remains in OPSHIFT until the DONE line is set by the PRead or PWrite
FSM.  When this happens, PCWR is asserted to clear the Datain register data
valid flags; the OK flag is cleared; the I/O Select line is set
low as required by the PBus protocol;  and the system transitions to the 
PINIT state.

\subsection{The PWrite FSM}

     The PWrite FSM transfers data from the Datain registers to CAM-8 over the
PBus.  Its operation is started with the assertion of the OK flag by the
PControl FSM.  Data writes continue until the entire data transfer from the
interface board to CAM-8 is complete. The PWrite FSM is shown in
Figure~\ref{pwrfsm}.

\subsubsection{The WRWAIT State}

\begin{figure*}
\psfig{figure=pwrfsm.ps,width=6in}
\caption{The PWrite FSM of the PFSM System.}
\label{pwrfsm}
\end{figure*}

    The WRWAIT state is the reset state of the PWrite FSM.  The system remains
in this state until it detects that the OK flag has been set and that a 
CAM write is required ie. that WR is active.  Once these conditions are
met, there is a transition to the PWR1 state. 

\subsubsection{The PWR1 State}

    In the PWR1 state, the PWrite FSM drives the high order 16 bits
of available data from the presently addressed Datain register over the PBus
by asserting PDRDATA.
When data is available (PDAV); the transfer is not complete (/DONE); and
the PBus can accept data (/EOFIN), EOFOUT is asserted.  The 
transfer length is decremented by PLDEC, and there is a transition to the
PWR2 state.  If the transfer is complete (DONE asserted), then there is a
transition back to the WRWAIT state.
Otherwise, the system remains in PWR1 until one of these conditions
are met.

\subsubsection{The PWR2 State}

    In the PWR2 state, the PWrite FSM drives the low order 16 bits
of available data from the presently addressed Datain register over the
PBus.  This is done by the assertion of PDRDATA and PDR2.  When the data
transfer is not complete (/DONE) and
the PBus can accept data (/EOFIN), EOFOUT is asserted.\footnote{PDAV does 
not need to be checked since it was already checked on the transition into PWR2.}  The 
transfer length is decremented by PLDEC, and there is a transition to the
PWR1 state.  If a non-immediate write is occurring, then PINC is asserted
to increment the PCTR counter.  In addition, PCWR is asserted if PRCO is
active so that the Data Ready inputs from the Datain registers are cleared.
These inputs will be enabled again when the SFSM loads the Datain registers
with new data.

If the transfer is complete (DONE asserted), then there is a
transition back to the WRWAIT state.
Otherwise, the PWrite FSM remains in the PWR2 state.

\subsection{The PRead FSM}

    The PRead FSM is responsible for reading data from the PBus into the
Dataout registers during a read from CAM-8.  Like the PWrite FSM, operation
of the PRead FSM is started with the assertion of OK by the PControl FSM.
Data is read until the entire transfer from CAM-8 to the
interface board is complete.  Figure~\ref{prdfsm} shows the bubble diagram
for the PRead FSM.

\begin{figure*}
\psfig{figure=prdfsm.ps,width=6in}
\caption{The PRead FSM of the PFSM System.}
\label{prdfsm}
\end{figure*}

\subsubsection{The RDWAIT State}

   The RDWAIT state is the reset state of the PRead FSM.  The system remains in RDWAIT until the
OK flag is detected and the WR input is not high.  
There is then a transition to the PDIR1 state.

\subsubsection{The PDIR1 and PDIR2 States}

     These states are used to change the PBus direction from write to read. The bus direction was write when the 
Opcode value was written to CAM-8.  A change of direction is therefore
necessary in order to read the contents of the selected CAM-8 register. 
The PRead FSM remains in PDIR1 until the PBus can accept new data.  It then
sets the PBus RD/WR line to read and transitions to the PDIR2 state.  The
setting of the RD/WR line enables counting of the Timeout counter.

     The system waits in PDIR2 for EOFIN to become unasserted as an indicator
that the bus direction has changed to read.  The explanation is as follows.
If the bus direction is write and the EOFIN has become low,\footnote{This
represents the conditional transition into PDIR2.} then the same
line cannot go back high again since EOFOUT is unasserted and no data is being
 sent over the PBus.
When EOFIN does go high again, it must therefore mean that the PBus node
adjacent to the interface board has assumed 
the default empty state that occurs with a bus transition from write to read.

     When EOFIN goes high, a transition is made to
the PRD1 state in preparation for reading the required data from CAM-8.


\subsubsection{The PRD1 and PRD2 States}

     The PRD1 and PRD2 states are used to read data from the PBus into the
Dataout registers.  Unless a timeout occurs, the system remains in these states until the entire 
read transfer is complete, at which time DONE becomes active.  When this
happens, there is a transition back to the RDWAIT state.  If a timeout 
occurs before the first assertion of /EOFIN, then the PFSM is reset, and
a host interrupt is activated.  The timeout is necessary to prevent the system
from hanging when an invalid module select ID has been sent to CAM.

     When DONE is unasserted, the system remains in PRD1 until the PBus contains
valid data and the Dataout registers are clear of valid data (/EOFIN*/PDRD).  In
this case, the PBus data is loaded into the high order 16 bits of the presently
addressed Dataout register by the assertion of
PLD1.  The length counter is decremented with PLDEC and the PBus data is
advanced by the assertion of EOFOUT.  The system then enters the PRD2 state.
Here the PRead FSM waits for more valid PBus data (/EOFIN).  When this data 
becomes
available, it is loaded into the low order 16 bits of the presently
addressed Dataout register by the assertion of PLD2. The data transfer length
counter is decremented by PLDEC, and the PCTR is incremented with PINC.  
EOFOUT is asserted to advance the PBus data.
 A transition
is then made back to PRD1.

     The loading of the final 16 bit Dataout register sets the DRD flag.  This
informs the SFSM that the Dataout buffer is full and that a burst write to
the host memory should occur.  Once this burst is complete, the SFSM clears
the PDRD flag so that the PFSM can resume loading the Dataout registers with
more data.  The assertion of DONE immediately sets the
DRD flag to the SFSM.

\subsection{The PEdge FSM}

    The PEdge FSM is responsible for asserting the EOFOUT line of the interface
board when the PBus can accept data and the Edge FSM of the parity generation 
chip is driving the parity word onto the PBus.  In addition, this FSM sets a
parity flag which prevents the PControl FSM from processing a new instruction
before the parity word of the last PBus data transfer has been sent to CAM-8.

\begin{figure*}
\psfig{figure=pedgefsm.ps}
\caption{The PEdge FSM of the PFSM System.}
\label{pedgefsm}
\end{figure*}

    Figure~\ref{pedgefsm} shows that the PEdge FSM is very similar to the
Edge FSM of the parity hardware.  Upon reset, the PEdge FSM enters the LOW
state.  The system remains in LOW until PIOSEL goes high.  At this point, the
parity flag is set and there is a transition to the HIGH state.  The PEdge
FSM remains in the high state until PIOSEL goes low again, when there is a
transition to TRANS.   The system waits in TRANS until EOFIN goes low.  This
indicates that the PBus can accept new data.  When EOFIN goes low, EOFOUT is
asserted low by the PEdge FSM.  At this time, the parity hardware will be
driving the parity word onto the PBus.  The parity flag is cleared and there
is a transition back to the LOW state.

\subsection{Implementation of the PFSM}

    All of the finite state machines of the PFSM were integrated into a
single Altera MAX5032 programmable chip.  Simulation of this chip with the
MAX System simulator showed that the required PFSM operation rate of 25MHz
could be met with the implementation.  The Altera Hardware Description 
Language (AHDL) text file for the PFSM is shown in Appendix C.

\begin{table*} 
\footnotesize    
\begin{center}

\begin{tabular}{|l|c|p{12.0cm}|}
\hline
\multicolumn{1}{|c|}{SIGNAL}
&\multicolumn{1}{|c|}{TYPE}
&\multicolumn{1}{|c|}{FUNCTION}
 \\ \hline

pb\_clk & Input & PBus clock line which serves as the clock for the PFSM. 
              \\ \hline
rst    & Input & Reset line for all FSMs in the PFSM system.
              \\ \hline
pdav & Input & Multiplexed data available signal to the PFSM.  Indicates that
the Control or Datain register referenced by the PCTR has valid data.
               \\ \hline
wr     & Input & Flag input from the instruction word. Indicates a write 
to or read from CAM.
              \\ \hline
done & Input & Indicates that the present instruction has been
executed.  This means that the data transfer specified by the
instruction has been completed.
              \\ \hline
immed & Input & Flag input from the instruction word. Indicates an
immediate write to CAM.
              \\ \hline
pdrd & Input & Indicates that the Dataout registers contain valid data 
and may not be loaded.
              \\ \hline
pseldone & Input & Indicates that all relevant Opcode register bits have
been sent to CAM.
              \\ \hline
prco & Input & Indicates that the PCTR contains the value 11.  This 
means that the final Datain or Dataout register is addressed.
              \\ \hline
eofin & Input & EOF status input from the neighboring PBus node.  This active
low line also stops the timeout counter.
              \\ \hline
ptyflg & Flag & Ensures that the PFSM does not shift new Opcode data over the
PBus until the parity word from the last data transfer has been transmitted to CAM.
              \\ \hline
ok & Flag & Indicates that the Opcode data has been shifted out over the PBus.
              \\ \hline
ldctl & Output & Loads the Opcode data from the Control registers into
a PFSM controlled shift register.  Also loads the transfer length into a
PFSM decrementable counter.  In addition, this signal clears the instruction
ready flag, enables the DONE flag, and clears the timeout counter.
              \\ \hline
ld & Output & Loads the PCTR counter with the value [/pc,pc,pc].
              \\ \hline
pc & Output & Determines the value to be loaded into the PCTR counter.  
The PCTR points to the Control, Datain or Dataout register addressed by
the PFSM.
              \\ \hline
pinc & Output & Increments the PCTR counter.
              \\ \hline
pcwr & Output & Clears the Data Ready inputs from the Datain registers.  This
effectively clears the PDAV line when the PCTR counter points to a Datain 
register.
              \\ \hline
piosel & Output & The I/O Select line of the PBus.
               \\ \hline
eofout & Output & The interface board EOF status output to its neighboring
PBus node.
              \\ \hline
psh & Output & The shift enable line for the shift register which shifts the
Opcode data out over the PBus data lines.
              \\ \hline
pdrdata & Output & Drives the contents of the presently addressed Datain
register as a 16 bit word on the PBus.
              \\ \hline
pdr2 & Output & Selects between the high and low order 16 bits of the currently addressed Datain register.
               \\ \hline
pld1 & Output & Loads the high order 16 bits of the currently addressed 
Dataout register with PBus data.
               \\ \hline
pld2 & Output & Loads the low order 16 bits of the currently addressed 
Dataout register with PBus data.
               \\ \hline
pldec & Output & Decrements the length of data transfer counter with 
each successful PBus data word transfer.
               \\ \hline
pbusdir & Output & The RD/WR line of the PBus.  This determines the direction
of data transfer over the PBus.  Enables the timeout counter in read mode.
               \\ \hline
\end{tabular}
\end{center}
\normalsize
\caption{Signals of the PFSM System.}
\end{table*}


