\section{The SFSM of the CAM-8 Interface Board}

    This section describes the SFSM that is used on the
interface 
board.  The SFSM controller operates at the SBus clocking rate and 
performs the following functions:

\begin{itemize}
    \item Fetches each Display List instruction from the host memory
          and loads it into the Control Registers for execution.
    \item Sequentially loads the Datain Registers with
          data from the host memory during a write to CAM.
    \item Sequentially drives the Dataout Registers over the SBus 
          when they are filled by the PFSM during a read from CAM.
    \item Halts execution of the Display List instructions when required
          to wait on a specified event.
    \item Handshakes with the PFSM for the most efficient operation of the
          board as a whole.
\end{itemize}

     The SFSM acts as a DVMA master whenever it interacts with the SBus.
Because of the complexity of the SFSM, it was necessary to break this finite
state machine into four separate finite state machines which all run in 
parallel.  A Control FSM is responsible for interpreting the Display List
instructions and setting the pointers that are used by the other FSMs.
A Parameter Drive FSM drives the initial virtual address and the SBus
{\sf Size(2:0)} and {\sf Read} lines at the required times.  A CAM-Write
FSM loads data from the SBus into the Datain registers during a write to
CAM.  Finally, a CAM-Read FSM drives data from the Dataout registers over
the SBus during a read from CAM.
State transition bubble diagrams for the operation of these finite state machines
are shown in Figures~\ref{ctlsfsm}, ~\ref{sfsm1} and ~\ref{sfsm2}.
The remainder of this section describes the operation of the
SFSM in terms of these diagrams.

\subsection{The Control FSM}

     As mentioned above, the Control FSM is responsible for interpreting
the Display List program contained in the host memory and setting pointers
to be used by the other finite state machines in the SFSM system.  Figure~\ref{ctlsfsm} 
shows the 11 state implementation of the Control FSM. 

\begin{figure*}
\psfig{figure=ctlsfsm.ps,height=8in}
\caption{The Control FSM of the SFSM System.}
\label{ctlsfsm}
\end{figure*}

\subsubsection{The INIT State}

     On the assertion of the system reset, the Control FSM enters the INIT 
state.  An 
initial instruction flag is set by the assertion of SINST, and the
FSM goes to the WAITST.

\subsubsection{The WAITST State}

  In the WAITST state, the Control FSM waits for the occurance of
a specified event before continuing its interpretation of the 
Display List.  Possible events include the assertion of the video HSYNC or 
VSYNC signal, the CAM-8 End-of-Scan interrupt or the host write signals. 
Once the event has been detected, there is a transition to either the
INSTRLD state or the MAINPRC state.

     An INSTRLD transition occurs if the
initial instruction flag is set.  This will generally only occur immediately
after the system reset.  SETWR is asserted to set the SBus {\sf Read} line
high, CINST clears the initial instruction flag, and 011 is loaded into
the SCTR so that it points to the address of the next Display List instruction.
In addition, the FST flag is set so that the instruction may be loaded by the
CAM-Write FSM into the Control registers. 

     A MAINPRC transition occurs if the initial instruction
flag is not set ie. when the WAITST was entered from MAINPRC.
This indicates a required wait for a condition before proceeding to interpret
the remainder of a previously fetched instruction.  The CLRENWT signal is
asserted to clear the enable wait flag so that the system does not re-enter
the WAITST after it transitions to MAINPRC.

\subsubsection{The INSTRLD State}

      In the INSTRLD state, the Control FSM prepares to do an instruction load
from the host memory.
It requests the SBus and waits 
until it is granted mastership of the bus.  When the {\sf Grant*} line
becomes unasserted, the {\sf Request*} line is asserted by the Control FSM. 
Once the board is
granted the SBus, there is a transition to the INSTRPRC state.  The SCTR 
is loaded with 000 so that it points to the first Control register to be 
loaded from the SBus.

\subsubsection{The INSTRPRC State}

    In the INSTRPRC State, the Control FSM waits until the CAM-Write FSM has
loaded the instruction into the Control registers.  If a Rerun acknowledgment
is detected, then the board must retry the transfer.  A transition is made
to the RRNWT1 state in this case.  If there is no Rerun acknowledgment, the
ENWT flag is set in INSTRPRC.  The ENWT flag allows the
system to wait for a condition before proceeding to execute the remainder
of the instruction that has been fetched.

    A successful instruction load is indicated by the unassertion of 
{\sf Grant*} without any Rerun acknowledgments.  In this case, there is a
transition to the MAINPRC state.  The SCTR is loaded with 001 so that the
virtual address of the host memory location to be accessed for a CAM read or
write is available to be driven on the SBus by the Parameter Drive FSM. 

\subsubsection{The RRNWT1 State}

    In this state, the Control FSM simply waits for the SBus controller to
unassert {\sf Grant*} to indicate an end to the present bus cycle.  Since
a Rerun acknowledgment has occurred, 011 is reloaded into the SCTR so that
the virtual address of the instruction to be read can be driven on the SBus
by the Parameter Drive FSM.  The system reenters INSTRLD when {\sf Grant*} is
unasserted.

\subsubsection{The MAINPRC State}

     The MAINPRC state is the main interpretive state of the Control FSM. 
 It is in 
this state that Control Register and PFSM flag data are interpreted to direct
the operation of the Control FSM.  If ERROR is detected\footnote{This will
indicate either a Late Error or Error acknowledgment in a previous SBus cycle.},there is a transition to INIT so that the host can investigate the situation.
ERRINT is asserted to inform the host of the error condition.

     If the ENWT flag is set and WAIT is high, then there is a transition to
WAITST so that the system can wait on the required condition before continuing
to execute the instruction.  

     If the DONE line is high, then the instruction
has been executed, and there is an transition back to INSTRLD so that a new
instruction may be loaded.  CLRDONE is asserted to clear the DONE line, SETWR
is asserted to reset the SBus direction if it had been changed, and 011
is loaded into the SCTR so that the address of the next Display List 
instruction is driven by the Parameter Drive FSM.  The FST flag is also set
to allow an instruction load by the CAM-Write FSM.

     If there is no bus grant and a non-immediate CAM write is to be executed,
 then {\sf Request*} is asserted to obtain mastership of the SBus.  If a
CAM read is to occur and either DRD or FST is set, then {\sf Request*} is 
also asserted.  In this case, the SBus direction is changed to allow a
write from the board to the host memory by the assertion of CLRWR.

     If {\sf Grant*} is detected and the WR flag is set, then the system has
been given permission to do a write from the memory to the board.  The 
Control FSM transitions to WRPRC1 to process the write.  To increase bus
bandwidth, all data writes to the interface board occur as atomic SBus 
transactions.  Thus, the Control FSM continues to assert {\sf Request*} when
given this initial {\sf Grant*}.  The SCTR is loaded with 100 so that the
first Datain register may be loaded from the SBus.

     If {\sf Grant*} is detected and the WR flag is not set, then a CAM read
is required.  The system transitions to the RDPRC state.  The SCTR is loaded
with 100 so that the first Dataout register may be driven on the SBus.

     If none of the above conditions hold, the system transitions back to 
the MAINPRC state and
waits for one of them to be met.  This will usually be the
case for a long immediate write to CAM-8, when the system waits in MAINPRC
until the PFSM completes the transfer and sets the DONE flag.

\subsubsection{The WRPRC1 State}

     In the WRPRC1 state, the Control FSM waits for the completion of the
first burst CAM write of the atomic transaction.  {\sf Request*} is asserted
in this state in accordance with the SBus requirement that this line be
asserted until the {\sf Grant*} for the second burst is detected.

     If a Rerun acknowledgment is detected, there is an immediate transition 
to the RRNWT2 state, from which the transaction will be retried.  If there
is no Rerun acknowledgment, the system waits until {\sf Grant*} is unasserted.
There is then a transition to WRPRC2.  The FST flag is cleared and the SCTR is
loaded with the value 001 so that the starting virtual address of the next 
burst of data may be driven by the Parameter Drive FSM.

\subsubsection{The WRPRC2 State}

     In the WRPRC2 state, the Control FSM waits until it receives the
bus grant for the second cycle of the atomic transaction.  While {\sf Grant*}
remains unasserted, {\sf Request*} is asserted as required for the atomic
protocol, and the Control FSM remains in the WRPRC2 state.  Once {\sf Grant*}
is asserted, there is a transition to the WRPRC3 state.  The {\sf Request*}
line is no longer asserted, and the SCTR is loaded with the value 100 so that
the first Datain register is addressed.

\subsubsection{The WRPRC3 State}

    In the WRPRC3 state, the Control FSM waits for the completion of the
second burst CAM write of the atomic transaction.  If a Rerun acknowledgment
is detected, then there is a transition to RRNWT2.  Otherwise, the system 
remains in WRPRC3 until {\sf Grant*} is deasserted, at which point it 
transitions back to MAINPRC.

\subsubsection{The RDPRC State}

    In the RDPRC state, the Control FSM waits for the completion of a
burst transfer from the Dataout registers to the host memory.  If a Rerun
acknowledgment is detected, there is a transition to RRNWT2 from which
the transfer may be retried.  Otherwise, the system remains in RDPRC until
{\sf Grant*} is deasserted, at which point it transitions back to MAINPRC.
CLRFST is asserted to clear the FST flag.

\subsubsection{The RRNWT2 State}

     In the RRNWT2 state, the Control FSM simply waits for the SBus controller
 to
unassert {\sf Grant*} to indicate an end to the present bus cycle.  Since
a Rerun acknowledgment has occurred during either a data read or write 
operation, 001 is reloaded into the SCTR so that
the virtual address of the host memory address to be accessed can be driven 
on the SBus
by the Parameter Drive FSM when the transfer is retried.  Note that since
DONE will not be set at this time, there is bound to be retry of the
transaction when the system reenters the MAINPRC state. 

\subsection{The Parameter Drive FSM}

     As mentioned above, the Paramater Drive FSM is responsible for driving
the virtual address at the beginning of an SBus transaction.  It also 
asserts the correct values on the SBus {\sf Size(2:0)} and {\sf Read} lines
throughout the transfer.  As shown in Figure~\ref{sfsm1}, this FSM is 
a simple two state machine.

\begin{figure*}
\psfig{figure=sfsm1.ps}
\caption{The Parameter Drive and CAM-Write FSMs of the SFSM System.}
\label{sfsm1}
\end{figure*}

\subsubsection{The WAITBG State}

    In the WAITBG state, the Parameter Drive FSM awaits the assertion of
the {\sf Grant*} line by the SBus controller.  Once this is detected, the
FSM immediately asserts SDR\_S to drive the required virtual address onto
the SBus data lines.  It also asserts DRPARAM to drive the {\sf Size(2:0)}
and {\sf Read} lines.  There is then a transition to the DRIVE state.

    The Control FSM will have correctly set the value of the SCTR on a
previous clock cycle so that when SDR\_S is asserted as described above, the
correct virtual address is placed on the SBus.  In like fashion, the 
Control FSM would have set the value to be placed on the SBus {\sf Read}
line in a previous clock cycle.

     The WAITBG state is the reset state for the Parameter Drive FSM.

\subsubsection{The DRIVE State}

    In the DRIVE state, the Parameter Drive FSM simply awaits the deassertion
of the {\sf Grant*} line.  While this line remains asserted, DRPARAM must
be asserted so that the SBus {\sf Size(2:0)} and {\sf Read} lines are
driven during the present bus cycle.  As soon as {\sf Grant*} becomes
unasserted, DRPARAM is unasserted, and the system transitions back to the
WAITBG state.

\subsection{The CAM-Write FSM}

    The CAM-Write FSM loads burst data from the SBus into the Control or 
Datain registers on the Interface board.  As shown Figure~\ref{sfsm1},
it is implemented as a three state machine.

\subsubsection{The IDLE State}

     In the IDLE state, the CAM-Write FSM waits for the presence of data
to be loaded into either the Control or Datain registers.  This is indicated
if the WR flag is set and there is a bus grant and word acknowledgment.
When these conditions are met, there are two possible operations of the
CAM-Write FSM.  

     If the previous contents of Datain registers have been 
driven to CAM-8; if this is the first update of these registers; or
if an instruction is being read, then
the data is loaded from the SBus.  Here either the DRW or FST flags are
active, and there is a transition to CAMWR.  SLD is asserted to load the
first word of the transfer into the Datain or Control register.  SINC 
increments the SCTR value so that the next SBus word will be loaded in the
following register location.  Finally, SCWR is asserted to clear the DRW 
flag.

     If the Datain registers are being updated and the previous contents
of these registers have not been cleared by the PFSM, then the interface
board must spill the data that is read from the SBus.  In this case, neither
FST nor DRW are active.  The CAM-Write FSM transitions to SPILL to spill the
arriving data.

    The IDLE state is the reset state of the CAM-Write FSM.

\subsubsection{The CAMWR State}

    The CAMWR state is used to load SBus data into either the Control or
Datain registers.  If a word acknowledgment is detected, the SLD and SINC
signals are asserted to load the data into the presently addressed register
and to increment the value of the SCTR pointer.  

    The CAM-Write FSM remains in the CAMWR state until either {\sf Grant*} is
deasserted or an error acknowledgment or Late error is detected.  The 
deassertion of {\sf Grant*} indicates the end of the burst transfer.   The
other two conditions imply that an error condition has been encountered.
Whenever any of these conditions are met, there is a transition to the 
IDLE state.  INCADR is asserted if the burst transfer has been successful
to increment the
Start Address of the data transfer by 16 bytes.

\subsubsection{The SPILL State}

     The SPILL state is used to complete the required master obligations
of the interface board when data is ready to be sent to it but the 
previous contents of the Datain Registers have not yet been sent over the
PBus.  The CAM-Write FSM merely waits in the SPILL state until {\sf Grant*}
 has been
deasserted.  At that time, the host will have sent the desired data but it 
would not have been 
stored anywhere.  The CAM-Write FSM transitions back to the IDLE
state.  Note that the Start Address has not been incremented.  Hence the
following SBus read will provide the same data.  Hopefully, the next time 
the data arrives, the Datain Registers will be able to accept it.

\subsection{The CAM-Read FSM}

     The CAM-Read FSM drives data from the Dataout registers on the
interface board to the host memory over the SBus. Figure~\ref{sfsm2} shows
that this FSM is implemented as a 6-state machine.

\begin{figure*}
\psfig{figure=sfsm2.ps}
\caption{The CAM-Read FSM of the SFSM System.}
\label{sfsm2}
\end{figure*}

\subsubsection{The START State}

     The START state is the reset state of the CAM-Read FSM.  The machine
waits in this state until it detects a bus grant with the write flag 
unasserted.  This would indicate that a read from CAM-8 is required.  When these
conditions are met, and provided that the error flag is not set, a transition
 to the CAMRD1 state occurs.  If the error flag is set or the above conditions
are not satisfied, the system remains in the START state.

\subsubsection{The CAMRD1 State}

     In the CAMRD1 state, SDR is asserted to drive the contents of the
first Dataout register onto the SBus data lines.  If an
Error acknowledgment or Late Error is detected, there is a transition back
to the START state.  If a Rerun acknowledgment occurs, the system goes to
the CAMRD5 state.  Finally, if a word acknowledgment occurs, SINC is 
asserted to increment the SCTR, and there is a transition to the CAMRD2
state.  If none of these hold, the system remains in the CAMRD1 state.

\subsubsection{The CAMRD2 and CAMRD3 States}

    These states are very similar to the CAMRD1 state, except for the fact
that there is no check for Rerun ac\-knowl\-edg\-ment.\footnote{This is justified since
the SBus specification indicates that a Rerun acknowledgment can only occur
as the first acknowledgment of a burst transfer.}  The CAMRD2 and CAMRD3 
states drive the contents of the second and third Dataout registers onto the
SBus.

\subsubsection{The CAMRD4 State}

     In the CAMRD4 state, the contents of the final Dataout register is
driven onto the SBus.  As above, if an Error acknowledgment or Late Error
is detected, there is a transition back to START.  In the CAMRD4 state, 
however, SDR is asserted only if a word acknowledgment is not detected.
This is necessary to conform to the SBus protocol requirement that the
SBus data lines be tristated on the cycle immediately following the 
final word acknowledgment.

     When a word acknowledgment is detected in CAMRD4, there is a transition
to the CAMRD5 state.  INCADR is asserted to increment the Start Address of 
the data transfer by 16 bytes, and SCRD is asserted to clear the DRD flag.

\subsubsection{The CAMRD5 State}

   In the CAMRD5 state, the CAM-Read FSM simply waits for the SBus {\sf Grant*}
line to be deasserted.  This formally indicates the end of the bus cycle.
The system then transitions back to the START state to await a new cycle.

\subsection{Implementation of the SFSM}

   A practical implementation of the logic for the SFSM machine presented a
challenging problem.  A programmable logic implementation was preferred so
that any bugs or changes to the interface board could be easily fixed.
Initially, a single SFSM was designed to perform the functions of the four
state machines described above.  The single SFSM was programmed into the
fastest available Xilinx programmable gate array\footnote{The Xilinx 3090 100MHz
chip was used.}.  Simulation of the chip, however, proved that it could not
operate at the required SBus 20MHz rate because of the complexity of the
logic and the high interconnect time of the Xilinx chip.  Indeed, the 
worst case delays through the system was well over 60ns versus the maximum
permissable delay of 50ns for a 20MHz system.

     An implementation in the Altera MAX5064 pro\-gram\-ma\-ble chip was also tried.
This appeared to work, although the worst case delay through the controller was
only a few nanoseconds short of the required operating period of 50ns.  This 
did not leave much margin for the addition of the datapaths of the interface
board.  

    At this point, the SFSM was partitioned into the four relatively 
independent systems described above.  It was possible to enter the
Control FSM in a single MAX5032 chip.  The Parameter Drive, CAM-Write
and CAM-Read FSMs could all be integrated into a second MAX5032 chip.
The MAX5032 part, apart from being smaller than the MAX5064, is also a much
faster chip.  Simulation of the partitioned SFSM with the Altera MAX simulator
proved that the required SBus rate of 20MHz could be readily achieved with
the MAX5032 parts.  The Altera Hardware Description Language (AHDL) text files
for the four finite state machines described above are shown in Appendix C.

\begin{table*} 
\footnotesize    
\begin{center}

\begin{tabular}{|l|c|p{12.0cm}|}
\hline
\multicolumn{1}{|c|}{SIGNAL}
&\multicolumn{1}{|c|}{TYPE}
&\multicolumn{1}{|c|}{FUNCTION}
 \\ \hline

sb\_clk & Input & SBus clock line which serves as the clock for the SFSM. 
              \\ \hline
rst    & Input & Reset line for all FSMs in the SFSM system.
              \\ \hline
sb\_bg  & Input & Active low SBus {\sf Grant*} line to the interface board.
              \\ \hline
ack(2:0) & Input & SBus acknowledge lines.  Used to decode word, rerun and
error acknowledgments.
              \\ \hline
wr     & Input & Flag input from the instruction word. Indicates a write 
to or read from CAM.
              \\ \hline
done & Input & Indicates that the present instruction has been
executed.  This means that the data transfer specified by the
instruction has been completed.
              \\ \hline
immed & Input & Flag input from the instruction word. Indicates an
immediate write to CAM.
              \\ \hline
wait & Input & Flag input from the instruction word. Indicates that 
execution must halt until a given wait condition has been met.
              \\ \hline
cond & Input & Multiplexed condition input specified for an instruction
wait.
              \\ \hline
drd & Input & Indicates that the Dataout registers have been loaded with
new data.
              \\ \hline
drw & Input & Indicates that the Datain registers can be loaded with new
data.
              \\ \hline
error & Input & Indicates that either an Error acknowledgment or Late Error
has occurred. 
              \\ \hline
instr & Flag & Indicates processing of first instruction after reset.
              \\ \hline
bsdir & Flag & Determines direction of SBus data transfer.
              \\ \hline
enwt & Flag & Enables halt of processing for a wait condition.
              \\ \hline
fst & Flag & Enables the loading of the Control registers.  Also permits
the Datain or Dataout registers to be initially loaded when DRW or DRD is
not set.
              \\ \hline
ld & Output & Loads the SCTR counter with the values specified on sc(2:0).
              \\ \hline
sc(2:0) & Output & Value to be loaded in the SCTR counter.  This counter 
points to the Control, Datain or Dataout register addressed by the SFSM.
              \\ \hline
clrdone & Output & Clears the DONE input to the SFSM.
             \\ \hline
br & Output & The SBus {\sf Request*} line for the interface board in master 
mode.
             \\ \hline
errint & Output & Interrupt line to signal that an error has
occurred on the interface board.
              \\ \hline
drparam & Output & Drives the SBus {\sf Size(2:0)} and {\sf Read} lines.
              \\ \hline
sinc & Output & Increments the SCTR counter.
              \\ \hline
sdr & Output & Drives the contents of the Dataout register addressed by
the SCTR onto the SBus {\sf Data(31:0)} lines.
              \\ \hline
sdr\_s & Output & Drives the contents of the Control register addressed by
the SCTR onto the SBus {\sf Data(31:0)} lines.
              \\ \hline
sld & Output & Loads data on the SBus {\sf Data(31:0)} lines into either
the Control or Datain registers.
              \\ \hline
scwr & Output & Clears the DRW flag input to the SFSM.
              \\ \hline
scrd & Output & Clears the DRD flag input to the SFSM.
               \\ \hline
incadr & Output & Increments the virtual address of the start of a data 
transfer by 16 bytes. 
               \\ \hline
\end{tabular}
\end{center}
\normalsize
\caption{Signals of the SFSM System.}
\label{stable}
\end{table*}




 
