\chapter{The Controller Chip I/O Protocols}

    This chapter describes some of the standard input-output protocols that
are used by the CAM-8 controller chip.  Although a sound understanding
of the chip hardware is not assumed, the reader may find it helpful to browse
over the hardware schematics when reading this chapter.

\section{The Register Bank Updating Protocol}
    
     This section describes the protocol that is used to update the
register bank of the input-output section of the CAM-8 controller chip. 
The typical unit of stimulation and update in CAM-8 is the space module.  As
described previously, a space module contains 16 controller chips, each with
its own register bank.  In a CAM-8 register access, the identical bit sequence
is first transmitted to all controller chips in a space module to select the
same input-output register in all of these chips.  Thereafter, during a
write operation, different data bits may be sent to the register in each chip.
For a read operation, different data contents can be expected from each 
controller chip. 

    In order to simplify the protocol and reduce the number of wires that
must be routed to the controller chips, information to each chip is serially
transmitted and received.  Two input-output lines are used by the interface
board for register update and readback --- the I/O Select line and the I/O Data
line.  A single I/O Select line is connected to all controller chips in a
space module.  Each controller chip is tied to a unique I/O Data line of the
16 bit PBus.

   The I/O Select
line is used to differentiate the updating of the Opcode register from that of
the 
data registers of the register bank.  A low on this line indicates that the
Opcode
register is to be accessed and a high indicates that the data registers are
addressed. The Opcode register stores
the address of the currently accessed register of the Register Bank.  The
I/O Data line serially transmits the contents of the Opcode register as well
as the actual data bits that are to be stored in the
registers of the register bank.  The protocol described in this chapter 
indicates which hardware
control signals are asserted for given changes in the I/O Select line.  It
also indicates at what times the I/O Data line must be guaranteed to contain
specific data.

\subsection{The Protocol}

  Based on the hardware design of the input-output section of the controller chip,
three distinct operations must be completed to facilitate register access:

\begin{enumerate}
   \item The Opcode register must be cleared.
   \item The Opcode register must be loaded with address data.
   \item The selected register must be enabled.
\end{enumerate}

    The first two operations load the selected address into the Opcode
register and the final operation enables the chosen register for input-output
access.

\subsubsection{Clearing the Opcode Register}

     The Opcode register is cleared to erase any previous contents that it
may have contained.  Since the address is transmitted with the least significant
bit sent last, low addresses may be loaded in fewer than the seven clock
cycles that it would normally take to fill the 7-bit Opcode register.  For
example, register 0 may be selected by simply clearing the Opcode register.

     The Opcode register is cleared when the I/O Select line transitions
from high to low.  As shown in Figure ~\ref{ioprtcl}, the clearing occurs 
during the clock cycle immediately following the fall
of the I/O Select line.  During this clock cycle, the parity word is sent
to the controller chip.  The chip checks that the parity bits are of the
expected values, and generates an interrupt if there is some error.  Immediately after reset, the Opcode register of the controller chip is automatically
cleared. 

\subsubsection{Loading the Opcode Register}

    Once the Opcode register has been cleared, it must be loaded with the
address of the register to be accessed.  This is done by serially shifting 
address data into the
Opcode register.  If the I/O Select line is low in a given clock cycle
and it was low in the previous clock cycle, then the Opcode register is
enabled.  The interface board must hold the I/O Select line low
for at least one clock cycle and for no more than eight clock cycles.\footnote{One clock cycle clears the Opcode register; eight clock cycles clear and fully
load it with new address data.}

   The I/O Data line must contain parity data on the clock cycle immediately
following the high to low transition of the I/O Select line.  It must contain
valid Opcode data from the second clock cycle
after I/O Select has gone from high to low until the clock cycle immediately
preceding the low to high transition of the I/O Select line.  This
data must be the serially transmitted register bank address to be selected.


    Once the Opcode register has been loaded and the I/O Select line goes 
high, the Opcode register acts as a counter to implement the auto-increment
feature for register access.  The enable line for the counting is derived
in the Counter logic of the controller chip.

\begin{figure*}
\psfig{figure=ioprtcl.ps,width=6in}
\caption{Time Line for the Register Bank Updating Protocol.}
\label{ioprtcl}
\end{figure*}


\subsubsection{Enabling the Selected Register}

   After the correct address has been loaded into the Opcode register, the
Enable logic block ``turns on'' the selected register.  This enabling 
occurs if the I/O Select line is high in a given clock cycle and the chip
is enabled.

   An enabled register programmed for write expects valid register data
to be serially transmitted  
on the I/O Data line.  Thus, valid data must be present on this line
by the clock edge immediately after the low to high transition of the I/O
Select line. The interface board must transmit just the right
number of data bits to match the size of the register that it has selected.  Of
course, in auto-increment mode more data can be sent to update the contents of
sequentially addressed registers.

   If the register is in read mode, then the I/O Data line will contain 
the high order bit of the selected register on the first clock edge
 after the low 
to high transition of the I/O Select line.  The remaining contents of the register
are serially transmitted out on subsequent clock cycles.

\subsection{Additional Details}

   A time line diagram illustrating the protocol described above is shown 
in Figure ~\ref{ioprtcl}.  The discussion has assumed the continual
enabling of the controller chip.  In reality, the chip is enabled only
in those clock cycles during which it has been selected for I/O and the PBus
node connected to it can send or receive data.  The protocol still holds,
 however, so long as
a ``clock cycle'' is taken to mean a chip enabled clock cycle.

\section{Initialization of the ID Registers of the Space Modules}

   Before an experiment can be run on CAM-8, every space module in the machine
must be assigned a unique identification number or ID.  This allows the software to uniquely select each space module for register access.  In addition, space
modules may be tagged together to form groups of modules.  The host
may then simultaneously write the same data to all modules in a given group. 
This saves the overhead of having to sequentially select all modules in a
group only to write the identical data to all of them.

   The ID and Group labelling of the space modules is programmed by the CAM-8
software.  This is advantageous since it eliminates the need for hardwiring the
modules.  Software control also provides the flexibility of changing the
system configuration from experiment to experiment. 
 Since a complete space module is the basic unit of selection in CAM-8, the
ID and Group numbers associated with a module are distributed over all 16
controller chips which make up the module.  Each space module has an associated 
16 bit ID register and a 16-bit Group register. One bit of these registers
is stored in each controller chip of the space module.  A corresponding
ID select and Group select register is also associated with each component
controller chip. A space module is normally selected for I/O when the ID select or Group
select registers of all the controller chips in the module match the programmed
ID or Group values.  Communication across the component chips of the space
module for the match comparison occurs through the use of a wired AND 
implementation.
All system modules may be selected in unison by the activation of a PBus
Broadcast line which is routed to every CAM-8 controller chip. 
 
    The assignment of ID and Group numbers presents the host with
the problem of selecting individual modules for initialization in the
absence of any unique information with which to turn on a module!  Indeed,
upon reset, all of the space modules in the system appear identical to the
host.  This problem is overcome as described below.  

   A module may be enabled for I/O if there is either a match or mismatch
between its programmed and selected ID or Group registers.  An Invert bit
in the register bank of the chip determines whether the module is selected
for an ID or Group match (Invert Bit = 1) or mismatch (Invert Bit = 0).
In addition, a module may be selected if the incoming glue line to that
module is at a specified logic level.
As mentioned above, normal operation corresponds to an Invert bit value of
1.  However, the mismatch and glue line selection are utilized in the initialization routine as follows.

   The host first broadcasts to all modules and writes an
 ID number of 0 to them.  It
then sets the Invert bit value of `0' as the selection condition.
The hardware is arranged so that the host is tied to the open collector
network of one of the space modules.  Now the host selects on the module with
ID number of 0.  Of course, all modules are deselected since their open
collector wired AND lines will remain high as a result of the match between
the programmed and selected IDs.  The host, however, pulls the open 
collector line that it is connected to low and forcibly selects one of the
space modules.  The correct ID number is written to this module and the
host instructs the module to send a `1' across its glue line to the module
to its right.

     Next, a broadcast occurs, and the host indicates a selection of the
module which receives a `1' on the glue line from its left neighbor.  The
Invert bit is reset to 1 for normal operation and the ID of the newly
selected module is written.  Now the host
broadcasts that all modules should send a `0' over their glue lines.
The host reselects the last ID updated module using its programmed ID 
and configures it to
write a `1' to its right neighbor.  A selection is now done on 
the module receiving a `1' from its left neighbor, and the ID number
of that module is written.  The procedure is repeated until every module in the entire sea of 
space modules is uniquely labelled.

\section{The Fast Sequential Readback Mode}

     A typical operation of the CAM-8 machine involves running an experiment
on it and then reading back the accumulated sums in the event counters.  Under
normal I/O operation, reading the event counters would require that the
 host sequentially
select each space module and then perform a read operation.  The host must
transmit the module ID to select a module and then read the event counter.
This process is inefficient because it involves transmitting sequential name
IDs and changing the bus direction twice for every event counter access. 
Changing the bus direction requires a holdup equal to the pipeline
latency of the bus.  It was therefore preferable that a special mode be 
designed to handle this situation more efficiently.  The Fast Sequential 
Readback mode involves using the Lookup Table address counter value to select a space 
module for readback.  There is no conflict of operation since this counter
will not be in use when an event counter readback is to occur. 

     A fast sequential readback is initiated by first loading the Opcode
 register 
with the address of the event counter.  The Module Select
hardware is programmed to enable a space module when its
ID register matches the value of the address counter of its Lookup Table.
In this mode, special circuitry increments the Lookup Table counters after
 25 bits
of data have been successfully transmitted over the PBus.\footnote{The 
event counter is 25 bits in length, so the Lookup Table counter is incremented
once for every event counter read.}   
The address counters of all of the Lookup Tables in the system are cleared and
enabled.
The system is then allowed to run. 
  The result is the sequential
transmission of event counter information from the space modules to the
host.  Although the Lookup Table counters in all modules count simultaneously,
only the selected space module will drive data to the host.  As soon as one
space module has completed sending its event counter data, it automatically
becomes deselected.  The module whose ID is one higher then starts to transmit
its event counter data to the host.  This continues until all event counters
in the system have been read by the host.

   

