Part II

System structure

7 Step machine and controller

7.1 Overview

A complete step system consists of a three-dimensional array of step boxes driven by a host via a tree-shaped network called the CBus, as sketched in Fig. 7.1 (where only two dimensions of the array are shown).

Figure 7.1: A step system consists of an array of step boxes (step machine) driven by a sparcstation (host). The step controller interfaces the host’s Sbus with the machine’s CBus.

In the current implementation, the host is a sun sparcstation, which features a high-performance external bus called the SBus. The CBus is driven at the root by the step controller—a small custom board plugged into one of the SBus slots. From this board, a short cable— which represents the CBus trunk—leads directly to one of the boxes, located on a corner of the array. From this corner box the CBus branches out through the rest of the array. We shall call step machine the interconnected array of step boxes, when viewed as distinct from the host and the step controller.

7.2 Hardware hierarchy

Each box of the step machine array realizes, by means of eight identical printed-circuit boards called modules, a functional block of eight sectors (see Chapter 3). Besides, the box provides mechanical and electrical support (motherboard, enclosure, power supply and cooling) to the modules themselves, as well as CBus routing and buffering and some other support circuitry.

In turn, each module contains, besides conventional dram and sram chips, sixteen copies of the stepchip—a custom vlsi chip that one may view as embodying the step architecture. In fact, each stepchip has complete control over one dram chip’s data and control lines; and, collectively, the sixteen stepchips have complete control over the sram chips’ data and control lines—as well as over transactions over the CBus. Thus, the stepchips repesent the “glue” that turns plain electronic commodities into sophisticated computing resources.

The present Part II discusses the step system at four levels of the design hierarchy, namely,

1. the step machine with its controller (this chapter),

2. the step box (Chapter 8),

3. the step module (Chapter 9), and

4. the stepchip (Chapter 10).

For each level, formal interface specifications (pinout and signal description) with the level above it are given.

The stepchip (Level 4) is seen by the programmer as a set of registers accessible via the CBus. Part III expands Chapter 10 by giving a complete programmer’s model of the stepchip: it systematically describes structure and functions of these registers, giving, whenever appropriate, a functional model of the hardware controlled by the registers themselves.

One may view the host sparcstation as representing Level 0 of the hierarchy. Its relevant hardware and system-software aspects are documented by sun Microsystems. Step-specific software is documented in the step Programmer’s guide and User’s guide.

7.3 The step controller

The step controller is a small board with, on one edge, a connector that plugs into one of the SBus slots. At the opposite edge of the card, a connector that shows through the rear of the sparcstation represents the root of the CBus.

The main raison d’être of this piece of hardware is to provide an interface between the two buses, and to do so in such a way as to lessen the requirements for real-time response from the host.

While the SBus and the CBus are both synchronous, and at present have roughly comparable bandwidths, they are timed by independent clocks which are typically running at different rates. Moreover, the number and nature of the control and data lines, the protocols, and the signals’ electrical specifications are quite different in the two buses.

The step controller requires bus-master as well as busslave capabilities.^{1} In fact, in order to decouple step from the poor and rather impredictable real-time response of standard unix, the controller’s normal operating mode is to act as a bus master and interpret according to the step machine’s timing requirements a list of commands (steplist) directly off the sparcstation’s memory, without going through the cpu. These commands would previously have been written to memory by the cpu at its own leisure.

The controller is addressed as a slave only at initialization time or to recover from runaway situations.

Depending on specific implementation choices, clocking for the step machine may be generated by the controller or by the machine itself. (A clock line running along the CBus trunk will carry a clock reference signal from the controller to the machine or vice versa.) In either case

• The interface between circuitry clocked by the SBus and circuitry clocked by the CBus lies within the controller, which has provisions for arbitrating between the two clocks.

• Tight synchronism (within a small fraction of the clock period) between logically contiguous modules is achieved by local phase-locked loops.

See §?? for details of clock distribution and synchronization.

The principles of operation of the step controller (i.e., how it interprets a “script” consisting of steplist commands, initiating and supervising any SBus or CBus transactions that may be called for) are explained in Chapter 4.

7.3.1 SBus signals

The step controller interfaces with the SBus by means of a standard SBus connector. Signal description and pinout can be found in The SBus Specification (specifically, Tables 2-1 and 3-8 of that manual). The following

♠ SBus signals are not used by the controller: [Any unused signals?]

7.3.2 CBus signals

The CBus runs from the step controller to the corner box (§7.7) and thence outwards from box to box (cf. Fig. 7.1 and Fig. 7.4) on short lengths of cable called hops. Each hop consists of a bundle of tranmission lines (cf. §7.6) carrying the following signals

CBus signals

direction  name
bidirectional Data[0:F] Data[0:F]
outbound  Reset*  Reset*
outbound  Sync  Sync
outbound  Frame*  Frame*
outbound  OH  Outbound Handshake
inbound  IH  Inbound Handshake
inbound  Status*  Status*
outbound  Scan*  Scan*

(7.1)

The hop that runs from the step controller to the corner box is called the CBus trunk.

Within a box, the CBus is further distributed by the motherboard to the eight modules according to the pinout of table (9.2), and from there to the sixteen chips of each module according to the pinout of table (10.6).

The various CBus lines are discussed in detail in Chapter 3.

The inner end of a hop (the one closer to the tree root) plugs into one of a box’s three CBus branch connectors (that’s where a new CBus branch is grafted onto the tree); the outer end plugs into a box’s CBus root connector (that’s where the box faces towards the tree root). According to this terminology, the connector through which the step controller drives the CBus trunk is a CBus branch connector. Its pinout is the following

CBus branch connector

type  name
B2 Data[0:F] Data[0:F]
O2 Reset*  Reset*
O2 Sync*  Sync*
O2 Frame*  Frame*
O2 OH  Outbound Handshake
I2 IH  Inbound Handshake
I2 Status*  Status*
O2 Scan*  Scan*

(7.2)

In the CBus trunk (§7.3.2), the Scan* line carries master-clock (§??) rather than scan-in-progress (§??) information.

7.3.3 CBus Sync

The CBus Sync line carries, encoded as 5-bit bursts on a background of all zeros, messages used for achieving synchronization between sweeps and scans of the step machine (§??) and, respectively, horizontal and vertical scans of a crt monitor (or similar external equipment). The possible messages are tabulated in (??).

1On the sparcstation-1, one of the three SBus slots only offers bus-slave capabilities, and cannot be used for this purpose. At any rate, this slot is typically dedicated to the graphics interface.

code message  recipient
1 00 1 0 HMON crt monitor
1 01 0 0 VMON crt monitor
1 10 0 0 HCAM step machine
1 11 1 0 VCAM step machine

The above messages are generated on the step controller as follows. Two ganged programmable counters, namely, the horizontal counter and the vertical counter (the latter is clocked by the rising edge of the former), produce the waveforms of Fig. 7.3. For each counter, “mark” and “space” lengths are independently programmable; as a consequence, one can independently set the period and the duty-cycle. HCAM, VCAM, HMON, and VMON are issued at the rising and falling edges of these waveforms, as indicated in Fig. 7.3.

Figure 7.3: Sync messages are issued on the rising and falling edges of the waveforms generated by the horizontal and vertical counters.

The HCAM message that would occur concurrently with a VCAM is superseded by the latter; the stepchip will infer an HCAM from the presence of a VCAM.

While the coincidence of VCAM with an HCAM is a logical necessity, the fact that also VMON exactly coincides with an HCAM (and supersedes the latter) is a nonessential feature of the present version of the step controller.^{2} Since the stepchip does not respond to HMON and VMON messages,^{3} a step scan that extends past VMON and is synchronized to HCAM (cf. §6.1) will be suspended for one horizontal counter period when VMON occurs.

7.4 The step machine

The step machine is an assembly of step boxes physically arranged and interconnected as a three-dimensional array. The three dimensions are labeled x, y, and z, and along each dimension the elements of the box array are sequentially numbered from 0 upwards. Thus, the corner box (§7.1), located at the origin of the box array, has coordinates ⟨0, 0, 0⟩, and in a system of 2×3×5 boxes the box on the opposite corner would have coordinates ⟨1, 2, 4⟩.

Along any of the three dimensions, the array need not extend for more than one box. In particular, machines consisting of a single box are viable (and we expect that they will be in quite common use).

Figure 7.2: The above codes, transmitted on a background of all zeroes, signal the appropriate times for a crt monitor to start horizontal and vertical scans, and for the step machine to start sweeps and scans. Each message consist of a start bit (‘1’), a two-bit field carrying the intelligence of the message, a parity bit, and a stop bit (‘0’).

2Note that the step controller could be replaced by, say, a video camera as a source of sync messages, in order to have video-on-video.

3Each stepchip monitors the integrity of all sync messages, by checking the parity bit, but otherwise ignores messages directed to the crt monitor.

A box interfaces to the outside world through three groups of signals, namely glue signals and CBus signals, which travel between boxes on transmission lines (§7.6) and turn the collection of boxes into a tightly-knit whole, and data stream signals, which offer optional access to the box’s internal data stream. In addition, there are a small number of signals used for configuration and test purposes. All these signals are described in detail in Chapters ?? and ??

The glue signals exchange, in real time, site data between adjacent sectors, according to the current datatransport specifications for each layer (cf. §2.10). Six glue ports are provided—each port corresponding to one of the six “faces” of the box, i.e., the six spatial directions in which a box can interconnect with other boxes, denoted by XM (“x minus”), XP (“x plus”), and similarly YM, YP, and ZM, ZP. Besides the data lines, each glue port includes two lines that exchange clock-phase information between adjacent boxes (§7.5).

The CBus signals ultimately connect the boxes to the host. Each box has one root port, facing inside (that is, towards the host), and three branch ports, facing outside in the positive x, y, and z directions. The root port is always used: the one on the corner box connects directly to the CBus trunk, the others, to bus hops that come from intermediate boxes. On the other hand, a branch port is used only if the box is the root of a subtree . Thus, for example, in a machine of size 2×2×2 boxes (see Fig. 7.4), the corner box ⟨0, 0, 0⟩ uses all three branch ports, box ⟨0, 0, 1⟩ uses only x and y, boxes ⟨0, 1, 0⟩ and ⟨0, 1, 1⟩ use only x, and the remaining four boxes, with addresses of the form ⟨1, y, z⟩, use none, since they are at the leaves of the tree.

Unlike glue signals and CBus signals, the data stream signals that appear on each box do not connect to other boxes; in fact, they do not need to be connected to anything in particular for the step machine to operate properly.

Through the Flywheel ports, external equipment can selectively extract any of the data involved in the simulation and optionally replace them with arbitrary new data; these lines are thus used for something like “local open-brain surgery” (it is unlikely that even the most advanced user will connect external equipment to more than one box).

Through the Video port, one can send to a color monitor and view in real time the contents of a selected step sector.

[figure: ⟨0, 0, 0⟩; x; y; z; ⟨0, 0, 1⟩; x; y; ⟨0, 1, 0⟩; x; ⟨0, 1, 1⟩; x; ⟨1, 0, 0⟩; ⟨1, 1, 0⟩; ⟨1, 0, 1⟩; ⟨1, 1, 1⟩]

Figure 7.4: CBus port usage in a 2×2×2 box machine. The dots represent boxes; the arcs, CBus hops. The x, y, z labels indicate to which branch port of a box the inner end of a hop is connected.

7.5 Clock distribution and synchronization

The current step implementation consists entirely of synchronous digital circuitry. Each box has its own local master clock, which drives the clock distribution tree for the entire box. The issue discussed here is the mutual synchronization of the local masters within prescribed tolerances.

Though the step array may extend arbitrarily in all three dimensions, its elements (the boxes, in the present context) are only locally interconnected. Thus, all that matters is that the clock phase difference between a box and each of its six neighbors (the ones with which the box exchanges glue data) be within tolerances. There will be no harm if, in moving from one box to the next along a given direction, these differences add up—leading perhaps to a cumulative phase difference of several clock cycles between widely separated boxes.

In step, local master clocks in adjacent boxes keep within tolerances with respect to one another by exchanging clock-phase information. This provides the feedback by which the phase of each individual clock is dynamically adjusted according to a phase-locked loop scheme: i.e., this phase is continually made to track (according to a suitable response function) the mean of the phases of its six neighbors.

♠

[Revise and partially scrap this] Usually, at the heart of a phase-locked loop there is a variable-frequency oscillator (VFO). The phase difference between the oscillator and the reference signal is used to pull the oscillator’s frequency in such a direction as to reduce this difference. However, since the phase is proportional to the integral of the frequency rather than the frequency itself, one obtains in this way a secondorder loop; such a loop imposes certain trade-offs between stability and agility of response.^{4} On the other hand, suppose that a signal having the desired frequency were distributed to all boxes, reaching each box with a different phase (owing to propagation delays through the distribution network). Then the secondary master could match its phase to that of its neighbors by means of a first-order loop where the phase is adjusted directly (rather than indirectly through the frequency), with improved response characteristics. Alternatively, the distributed reference frequency could be used to adjust the VFO natural frequency, so as to minimize the amount of error feedback needed to pull the oscillator into phase lock.

Though the details of the local masters’ strategy for achieving phase lock are left unspecified, a single reference frequency may be made available to all boxes through a CBus Master Clock signal originating from the step controller. This signal could be used directly as the local master clock by the corner box, which would ignore phase feedback from its neighbors and would thus force them to do all the necessary adjusting. By directly using a copy of the Master Clock as a local master, “bare bones” boxes designed to work only in small machines (one to eight boxes) could dispense with the phase-locked loop altogether.

It may be decided at a later time to use the oscillator of the corner box as the primary master. In this case, on the CBus trunk the Master Clock signal would run from the corner box to the controller (rather than the other way around).

7.6 Interbox communication

Within a box, signals run short distances; they have a stable and uniform voltage reference provided by the modules’ and the motherboard’s ground plane; they are shielded from one another by the close proximity of the ground plane, and from external fields by the box’s enclosure. In this environment, a signal line, even though it may extend and branch out over several inches, can still be usefully treated as a voltage node.

Communication between boxes takes place in a rather different environment. The physical length of the lines from driver to receiver may run up to a few feet; glue lines run in parallel bundles of over a hundred lines each;^{5} each box is the source or destination of about a thousand 30-Mbit/sec signals; and boxes will typically be tied together by a mesh of ground bars or ground strips several inches in length rather than by a continuous copper plane. For these reasons, it is desirable to have interbox signals travel on well-characterized transmission lines, which feature low dispersion and (when properly terminated) low reflections, good common-mode noise rejection, and good decoupling between adjacent signals.

Though implementation details for transmission-lines, line-drivers, and line-receivers are left, for the moment, unspecified, we shall assume that each transmission line consists of a pair of wires (such as the two elements of a twisted-pair line, or core and shield in a coaxial cable). Accordingly, for each signal handled in this way we shall provide two separate pins on the connectors where the transmission lines terminate (cf. §9.1).

7.7 Corner box

Because of its unique position—at the origin of the step box array and at the origin of the CBus distribution tree—the step machine’s corner box plays a distinguished role in certain setup and housekeeping functions.

The step modules come out of power-up with all activity on their CBus branch ports disabled (see §6.21); thus, while the controller can communicate with the corner box, all other boxes are cut off from the CBus for the time being. Moreover, module 0 of a box is physically distinguished from the other modules of the same box by having the Multipurpose Pin A of stepchip 0 pulled down by an external resistor, so that its module ID at power

4Intuitively, in a second-order loop the phase has inertia that needs to be damped. If is overdamped, it will never reach the mark; if it is underdamped, it will overshhot it.

5Sixteen layers times eight strands gives 128 lines, to which one must add two clock-phase feedback lines.

♠ up will be FFFE rather than FFFF.[Norm, confirm this]

Taking advantage of the above features, the host runs an initialization procedure that systematically assigns module IDs, starting with 0000 for module 0 of box 0 (cf. §3.14). Once the corner box’s privileged geographical position has been recorded in distingushed IDs for its modules, the other boxes are gradually brought into communication with the CBus, proceeding outwards from the corner box.

The local master clock of the corner box ignores clockphase information coming from the adjacent boxes (cf. §??), and thus forces the latter to match their phases with its own.

If a reference clock signal is distributed along the CBus (cf. end of §7.6), the corner box may send rather than receive this signal on its CBus root port, thus clocking the step controller rather than being clocked by it.

7.8 Block wiring

In the present realization, a step module consists of a board having all of its connectors on one edge, as in Fig. 7.5, and a step block will consist of a box containing a card cage with a backplane where eight of these boards can be plugged in.

[figure: x_{−}; x_{+}; y_{−}; y_{+}; z_{−}; z_{+}]

Figure 7.5: Step module board, showing the six glue port connectors.

For such a realization of a step block, table (3.2) can be interpreted as a template for the backplane, indicating the eight slots (horizontal rows) and, for each slot, the position of the six glue-port connectors.

Using this template, Fig. 7.6 shows in its essentials the actual wiring between boxes. We only show the wiring for strand 0, and then only for the x and y dimensions (the wiring for the z dimension would go “through the page”).

Still using template (3.2), Fig. 7.7 shows the actual placement of the shorting plugs (cf. Fig. 3.5) at the edges of the array (using an array that is two blocks deep in

Figure 7.6: Backplane wiring for an indefinitely extended array of step boxes, with no wraparound. Four boxes are shown, and only the wiring for strand 0. The arrow direction goes from a ‘+’ port to a ‘−’ port (cf. table (3.2)).

Figure 7.7: How strands are connected at the edges of the array to form loops.

both the x and y dimensions; as in Fig. 7.6, the z interconnections are not shown). With these plugs, strand 0 forms a single loop with strand 1 in the x dimension, and with strand 2 in the y dimensions (in the z dimension, it would loop back as strand 4).

7.8.1 Single-block wiring

For a small step system consisting of just one block (eight modules), each dimension exhausts itself within the block, as indicated by the following diagram for just the x dimension

[figure: x_{−}; x_{+}; x_{+}; x_{−}],

and the complete wiring diagram will appear as in Fig. 7.8.

[figure]

Figure 7.8: Complete backplane wiring for a step system consisting of a single block.

7.8.2 Block wiring, improved

Each of the “wires” shown in Fig. 7.6 or Fig. 7.8 is actually a collection of 16 lines (one per layer), and typically will be implemented by a shielded flat cable. Since such cables are stiff and bulky, it is desirable to route them as neatly as possible, trying to keep them flat and parallel and avoiding repeated crossings.

By systematically rearranging the order of modules within a box and the order of ports within a module it is possible to arrive, for a single block, at the wiring pattern of Fig. 7.9, to be constrasted with that of Fig. 7.8. The improved wiring is arrived at as follows.

Port swapping. Fig. 3.5 suggests that, if strand 0 loops back as strand 1 in the x dimension, it would be more convenient if the modules of strand 1 had their x_{+}, x_{−} ports arranged in the opposite order as those of strand 0. More generally, a similar argument holds for the udimension ports (u = x, y, z) of any pair of strands whose labels differ only in the s_{u} digit (cf. (3.2)).

In order to respond to design requirements of the above kind, in a step module the correspondence between logical ports (x_{+},x_{−}, etc.) and physical ports (the six connectors at the bottom of Fig. 7.5) is software assignable rather than hardwired (cf. §6.22). Taking advantage of this feature, one can make the two x ports appear on the edge of the board in the order x_{−}, x_{+} or x_{+}, x_{−}, depending on whether the s_{x} bit is 0 or 1 (and similarly for y and z), leading to the following backplane template

strand  ports
s_{x}s_{y}s_{z} S x  y  z
000 0 −+ −+ −+
100 1 +− −+ −+
010 2 −+ +− −+
110 3 +− +− −+
001 4 −+ −+ +−
101 5 +− −+ +−
011 6 −+ +− +−
111 7 +− +− +−

(7.3)

Strand swapping. Finally, we shall permute the boards in the backplane’s eight slots so that the strand labels S are ordered according to Gray code rather than straight binary code:

strand  ports
s_{x}s_{y}s_{z} S x  y  z
000 0 −+ −+ −+
100 1 +− −+ −+
110 3 +− +− −+
010 2 −+ +− −+
011 6 −+ +− +−
111 7 +− +− +−
101 5 +− −+ +−
001 4 −+ −+ +−

(7.4)

It is easy to verify that the port-and-strand arrangement of template (7.4) indeed leads to the improved backplane wiring pattern given in Fig. 7.9. Similar methods can be used to streamline backplane wiring in more complex situations, such as that of Fig. 7.7.

[figure]

Figure 7.9: Improved backplane wiring for a step system consisting of a single block.

8 Step box

8.1 Overview

As we explained in Chapter 3, when a three-dimensional torus is flattened onto three-dimensional space, eight separate strands of the torus are brought together. A step box is responsible for simulating the activity of a step block, i.e., a sector-size window cutting through all eight strands (cf. Fig. 3.7). The entire torus can then be simulated by arraying in a straightforward way an appropriate number of boxes in the three dimensions of ordinary physical space.^{1}

Besides the resources directly devoted to the simulation (site-data transport and interaction), a step system makes uses of other resources (e.g., clock distribution, communication with the host) that must somehow be distributed and interconnected in an indefinitely expandible way within the same geometric framework as the blocks. It is natural to lump such resources on a per-block basis and incorporate one lump in each box. Thus, while the module represents the smallest repetitive unit of step from a functional viewpoint, in physical terms it is the box that represents the smallest repetitive unit—from which an arbitrarily large step system can be built by mere juxtaposition and nearest-neighbor interconnection.

Physically, a step box is a roughly cubical enclosure containing a regulated power supply and a motherboard with eight slots—for up to eight step modules. Additional circuitry on a per-box basis is present on the motherboard. Though, for convenience, some or all of this circuitry may reside on a card that plugs into a ninth slot of the motherboard, we shall still refer to it as ‘motherboard circuitry’.

As outlined in §7.4, a box interfaces to the outside world through three groups of signals, namely glue signals and CBus signals, which travel between boxes (§7.6), and data stream signals (data flywheel and video output), which allow external equipment to have real-time access to the box’s internal data stream.

The signals of each group are bundled into one or more ports according to their geographical destination. Thus, the glue signals are divided into six glue ports according to which of the six adjacent boxes they connect to. Each port, in turn, is physically represented by one or more connectors into which cable headers may be plugged. For convenience, also configuration and test signals are grouped together and brought to connectors.

In the present implementation, all of the above connectors (which deal with those signals that the box makes available externally) are on the motherboard, independently of whether the signals themselves are generated (or received) by motherboard circuitry or by circuitry on the individual modules.

Fig. 8.1 gives a simplified backview of the motherboard, showing the individual connectors and their groupings as ports. The modules plug in on the other side of the motherboard, and many of the port connectors are just through-the-board extensions of connectors on the modules.

8.2 Glue ports

Each module contributes to its box six glue connectors (XM glue through ZP glue; cf. Fig. ?? and Fig. 9.1) for bidirectional communication between adjacent sectors. On the box, each glue port brings together a set of eight homologous connectors (one from each module), so that, for instance, the eight XM glue connectors come together as the box’s XM glue port (Fig. 8.1). Each glue port has, in addition, a small connector with two signals (Clock Phase In and Clock Phase Out), handled by the motherboard circuitry, which exchange clock phase information between the local clock masters (cf. §7.5) of adjacent boxes.

Thus, between the XP glue port of a box and the XM glue port of the box next to it in the positive x direction there will run 128 bidirectional glue lines (16 layers times 8 strands) plus 2 clock-phase lines, for a total of 130 signal lines.

Note that the six physical directions XM, XP, …, ZP are distinct from the six logical directions, denoted by x_{−}, x_{+}, …, z_{+}, which refer to the orientation of an individual strand. Typically, the XM glue port will be configured as an x_{−} port by four of the modules in a box, and as an x_{+} port by the remaining four (cf. Fig. ??). A more general remapping of logical ports to physical ports is possible; for instance, when the three-dimensional array of modules is configured as a pleated two-dimensional array (§??), a Z port may be used to carry y information.

On each of the external faces of the parallelepiped— where a box is not mated to an adjacent box—four of the strands double back on the other four via the glue signals. For example, on an XM face, the four XM glue signals that carry x_{−} information (cf. Fig. ??) for a certain layer will fold back onto the corresponding four XM glue signals that carry x_{+} information. This is done by a passive

1Note that while the eight strands that run through the boxes are interconnected so as to yield the topology of a torus, the physical array of boxes forms an ordinary parallelepiped: opposite faces don’t have to be brought together!

Figure 8.1: Simplified backview view of the step-box motherboard. Dotted lines delimit ports, each consisting of one or more connectors. The small connectors on the glue ports are for clock-phase feedback between adjacent modules.

shorting plug or by an internal multiplexer (cf. §??). In a similar way, a Clock Phase Out signal that emerges from an external face of the parallelepiped is looped back into the corresponding Clock Phase In pin.

8.3 Data flywheel ports

On each stepchip, real-time (“on-the-fly”) access to the internal data stream is provided by two taps on this stream, namely Data Flywheel Output and Data Flywheel Input (§??). On the module, these sixteen outputs and sixteen inputs are brought together on a Data Flywheel connector (Fig. 9.1) together with the appropriate timing signals. In turn, this connector is passed through to the motherboard as a Data flywheel port, for a total of eight such ports (Fig. 8.1).

Data flywheel access is optional, and is provided for advanced experimentation, custom applications, attachment of custom hardware, specialized display or analysis needs, and in-depth testing and diagnostics.

As implemented in the standard step box described here, the Data flywheel ports are meant to provide direct real-time access to simulation data from any one module of a step machine, or at most a few modules: it would be physically impractical to connect external equipment to all modules at once. On the other hand, using specially designed boxes, it would be feasible to use the Data Flywheel connectors to add an external “coprocessor” to each module or group of modules.

8.4 Video port

A separate Video tap (§10.2.5, §??) on each stepchip’s internal data stream extracts data intended for real-time video display. On a module, these sixteen signals are brought out to the Raw video connector (Fig. 9.1). On the motherboard, the sixteen Raw video signals are bussed across the eight modules of a box (cf. §8.6); only one module at a time will have its tri-state bus drivers enabled. The Video port on the motherboard provides a buffered version of these sixteen raw-video signals, together with horizontal and vertical sync signals suitable for driving a crt monitor.

Signal conditioning circuitry on the motherboard takes in the raw video signals and puts out, throught the Video connector, appropriately formatted video output (such as analog and Horizontal and Vertical Sync).

It is desirable to turn the raw video into analog Red, Green, and Blue suitable for a standard color monitor, by means of a downloadable color palette and digital-to-analog converters. Though these functions may be provided by external circuitry having access to buffered raw video, eventually they should be provided by the motherboard itself. At any rate, pins for rgb output are reserved on the Video port.

Typically, a dedicated crt monitor permanently connected to the Video port of one of the boxes will be used to provide a real-time, sector-size window on the simulation data; this window can be panned at will through the site array.

8.5 CBus ports

A box also acts as a relay for CBus signals (§??), receiving the CBus via a CBus root connector on the motherboard and fanning it out to up to three adjacent boxes (in the XP, YP, and ZP directions) via the CBus branch connectors (Fig. 8.1). Since CBus relaying is done by the modules of behalf of the box, there are on the motherboard eight connectors (one on each module slot) available for the CBus branch function, with the potential for fanning the CBus out to eight boxes. However, no more than three of these connectors are used, since CBus distribution is organized on a three-dimensional tree basis (cf. §7.4).

8.6 Local bus

Besides relaying the CBus to other boxes via the CBus branch ports, the motherboard also conditions and distributes the CBus signals to the eight modules. This is done through a local bus (see Fig. 8.1), which also collects Raw video signals from the modules (§8.4), distributes the clock, and perform a number of miscellaneous functions.

8.7 Configuration and diagnostics

Finally, there are on the motherboard a number of pins used for configuration, testing, and diagnostics.

9 Step module

Physically, a step module consists of a printed circuit board which plugs into a slot of a step box motherboard (see §8.1) by means of a row of high-density edge connectors. The overall interconnection pattern for a box consisting of a motherboard and up to eight modules is sketched in Fig. 8.1 from the viewpoint of the motherboard, and in Fig. 9.1 from the viewpoint of a module.

9.1 Module pin types

The pins are sorted into functional groups, each of which is discussed in a separate section. In the pinout table in each section, the table header gives the total number of pins in the group and a descriptive name for the group itself (CBus interface, glue, video, etc.). For each pin, the tables give the pin type, according to table (9.1), and the pin’s mnemonics followed by its full name.

Module pin names are distinguished by the prefix ‘M/’, to avoid confusion with stepchip or box pin names.

As mentioned in §7.6, communication between step boxes (as well as between the controller and the corner box) takes place on transmission lines. The present pinout specifications are compatible with either unbalanced (e.g., coax cable) or balanced (e.g., twisted pair) transmission lines. In either case there are a pair of pins associated with each signal. Depending on the implementation, the two elements of the pair would be called “tip” and “ring,” “core” and “shield,” “signal” and “return,” “plus” and “minus,” or similar names. Here we’ll use the noncommittal designators ‘A’ and ‘B’.

In the pinout tables below, a signal-type designator ending with the character ‘2’ (cf. table (9.1)) denotes a transmission line pair, listed as a single entry but with the understanding that two pins are involved. Thus, an entry of the form

O2 M/FB* M/Frame Branch*

implies the existence of two pins, namely M/Frame Branch A* and M/Frame Branch B*.

Some of the transmission lines terminate on the motherboard (CBus root lines in Fig. 9.1), where they are handled by discrete drivers and receivers appropriate to the type of line. Most of the transmission lines, however, terminate directly on the module boards (e.g., XM glue or CBus branch in Fig. 9.1) and are associated with individual stepchip pins. If these pins have sufficiently powerful internal drivers, they will be able to drive unbalanced transmission lines directly, i.e., without the need for separate discrete drivers. In what follows, we shall assume that this is the case; however, the module pinout will not change if discrete drivers are inserted between the stepchip pins and the transmission lines, and/or if balanced transmission lines are used.

Note that the pins of motherboard connectors XM glue through ZP glue and Tbus branch (cf. Fig. 9.1) are not connected to any signal traces on the motherboard;^{1} they simply provide mechanical support and passive feedthrough from the modules to the transmission lines.

type  description

I Input. Input signal driving a discrete on-board buffer which fans out the signal to the sixteen stepchips of the module.

O Output. Output signal driven by the Low-Drive Multipurpose Pin of one of the sixteen stepchips.

B Bidirectional. This pin is sensed as an input, and is driven as a tri-state output.

I2 Input pair. Pair of pins (A and B) at the receiving end of a transmission line.

O2 Output pair. Pair of pins (A and B)

driving a transmission line. B2 Bidirectional pair. Pair of pins (A and B) which may drive or sense a transmission line.

(9.1)

9.2 CBus interface

CBus local

type  name
B Local.D[0:F] Local Data[0:F]
I Local.Reset* Local Reset*
I Local.Sync* Local Sync*
I Local.Frame* Local Frame*
I Local.OH  Local Outbound Handshake
O Local.IH  Local Inbound Handshake
O Local.Status* Local Status*

(9.2)

1In the case of unbalanced transmission lines, the B side of each pair would probably be tied to the ground plane.

Figure 9.1: Overall interconnection pattern for the modules in a step box. On the motherboard, the six glue connectors (XM glue thru ZP glue) devoted to each module—for a total of 48 connectors—carry plain feed-through pins: the signals go directly from a module in one box to a module in an adjacent box via a transmission line. The situation is similar for the CBus branch signals, where, however, only at most three of the eight connectors are used (to extend the CBus tree in the x, y, and z directions). There is only one CBus root connector, on the motherboard; outbound signals arriving at this connector are fanned out by the motherboard and distributed to the eight modules via the local bus connectors (one per module); similarly, inbound signals from these connectors are ored into a single CBus root signal by the motherboard. The Video connector on the motherboard produces video information gathered from the modules via the local bus.

CBus branch

type  name
B2 Branch.D[0:F] Branch Data[0:F]
O2 Branch.Reset* Branch Reset*
O2 Branch.Sync* Branch Sync*
O2 Branch.Frame* Branch Frame*
O2 Branch.OH  Branch Outbound Handshake
I2 Branch.IH  Branch Inbound Handshake
I2 Branch.Status* Branch Status*

(9.3)

The CBus local signals are handled by the motherboard, which fans out to the eight modules signals coming from the host (CBus root connector), and ors signals from eight modules into a single hostward signal.

The CBus branch signals represent the place where a subtree of the CBus tree can be grafted.

9.3 Glue

Glue

type  name
B 2 Glue0.G[0:F] Glue X-Minus[0:F]
B 2 Glue1.G[0:F] Glue X-Plus[0:F]
B 2 Glue2.G[0:F] Glue Y-Minus[0:F]
B 2 Glue3.G[0:F] Glue Y-Plus[0:F]
B 2 Glue4.G[0:F] Glue Z-Minus[0:F]
B 2 Glue5.G[0:F] Glue Z-Plus[0:F]

(9.4)

These are the signals that allow one to glue modules edge-to-edge so as to achieve an array of indefinite extent. Each glue signal runs point-to-point (no fan-out or fan-in) between two modules; in a large system, the two modules will reside in different boxes.

9.4 Data stream

Data flywheel

type  name
Out Flywheel.O[0:F] Flywheel Data Output[0:F]
In Flywheel.I[0:F] Flywheel Data Input[0:F]
Out Flywheel.Clock Flywheel Clock
Out Flywheel.DSV* Flywheel Data Stream Valid*

(9.5)

Raw video

type  name
IO Local.Video[0:F] Local Video[0:F]

(9.6)

9.5 Wired-AND communication

62

10 stepchip

Fig. 10.1 shows in a very schematic way the logical organization of a stepchip, especially in relation to the chip’s immediate surroundings.

glue to adjacent modules

raw video bus

data flywheel

CBus sram ...

scan generator

CBus interface

[figure] [figure] [figure] [figure] [figure] [figure]

data stream

dram

[figure]

ModSel [figure]

Int*

stepchip

other step chips in the same module

Figure 10.1: Logical organization of a stepchip and its immediate surroundings. See text for details.

Some of the stepchip’s i/o lines (§??) connect it to other circuitry on the same module, some to homologous stepchips on adjacent modules, some to the CBus, and some to optional external circuitry. These different types of interconnection are better understood with reference to the stepchip’s functions, as detailed below.

Though physically residing on a separate memory chip, the block labeled dram should logically be treated as part of the stepchip, since all of its inputs and outputs are directly handled by the latter.

The main function of the stepchip is to pump a data stream out of and then back into the dram. Along its course, the data stream may be modified by

• Data exchanges with adjacent modules, via the glue lines, to achieve indefinite spatial extension for the array of sites.

• Real-time data exchanges with optional external circuitry, via the data flywheel (§??).

• Real-time output to a raster-scan monitor, via the raw video bus (§??). All modules tristate their video lines onto a single Raw video bus, so that video output from any single module can be routed to the monitor.

• Data replacement by lookup in the sram table. The table is shared by the 16 stepchips of a module, each of which provides one bit of the lookup key (table address) and and receives one bit of the corresponding entry (table data). Of course, this collective lookup is the main mechanism for interaction between data streams, and ultimately for the realization of the desired dynamical behavior as well as of real-time analysis.

The CBus (Chapter 3) is the exclusive channel of communication between the host and the step modules. All exchanges between the host and sram or dram chips are mediated by the stepchip.

Beside being mutually coupled via the sram table, the 16 stepchips of a module are also mutually coupled via a wire-and ModSel line for the purpose of responding as a single addressable entity to CBus operations (§3.13), and a wire-and Int* line for collecting interrupts from the sixteen chips and eventually merging them onto the CBus Status line.

10.1 stepchip block diagram

The internal structure of the stepchip shown in Fig. 10.1 is further detailed in Fig. 10.2, which is taken from the stepchip’s actual design files (this diagram does not show the i/o buffers that interface the internal signals to the outside world).

10.2 Pinout

10.2.1 Chip pin types

The step chip is packaged in a 68-pin PLCC.

The pins are sorted into functional groups, each of which is discussed in a separate section. In the pinout table in each subsection, the table header gives the total number of pins in the group and a descriptive name for the group itself (dram interface, CBus interface, etc.). For each pin, the tables give the pin number, its type, according to table (10.1), and then the pin’s mnemonics followed by its full name.

Figure 10.2: stepchip block diagram, taken from actual design files.

64

type  description

I Input. This pin is sensed as an

input. O Output. This pin has an

output driver, which is always enabled.

T Tri-state. This pin has an out-

put driver which can be disabled. B Bidirectional. This pin is

sensed as an input, and is driven as a tri-state output.

W Wire-and. This pin is driven in a way suitable for wire-anding.

(10.1)

10.2.2 DRAM interface

Dram interface

type  name
O DA(10:0) DRAM Address(10:0)
B DD(3:0) DRAM Data(3:0)
O DRAS*  DRAM Row Address Strobe*
O DCAS*  DRAM Column Address Strobe*
O DWE*  DRAM Write Enable*
O DOE*  DRAM Output Enable*

(10.2)

These are the address, data, and control signals for the dram chip associated with each stepchip.

Since we use nybble-wide chips, total dram capacity with 11 address lines (DA(10:0)) is 4 · 2^{2·11}, or 16 Mbits.

Once we are in fast-page or static-column mode, typically a dram read/write operation takes 4 clock cycles; in the first two, a nybble is read, in the second, a nybble is written.

10.2.3 SRAM interface

Sram interface

type  name
O SA0 SRAM Address, Bank 0
O SA1 SRAM Address, Bank 1
B SD0 SRAM Data, Bank 0
B SD1 SRAM Data, Bank 1

(10.3)

These are the address and data signals for the two sram lookup tables, lut0 and lut1. The sram control signals are distributed on a module-wide basis by means of four of the Multipurpose pins (§6.21).

10.2.4 Glue

Glue

type  name
B XM X-Minus
B XP X-Plus
B YM Y-Minus
B YP Y-Plus
B ZM Z-Minus
B ZP Z-Plus

(10.4)

These are the signals that allow one to “glue” modules edge-to-edge so as to achieve an array of indefinite extent.

10.2.5 Data stream

Data stream

type  name
O FDO Flywheel Data Output
I FDI Flywheel Data Input
T Video Video

(10.5)

At every step, the entire dram contents (or whatever fraction of it is actually used for the model’s state variables) is serially made visible to the outside world via the Flywheel Data Output pin, before being sent to the lookup table. External circuitry can use these data for analysis purposes; and can replace any of these data bits with externally supplied ones. On every clock cycle in which Enable* is asserted, the internal data bit is replaced with one that is externally supplied via the Flywheel Data Input pin. The timing of this injection—either one or four clock cycles^{1} later than when the original bit appeared on the FDO pin—allows for the original bit to be taken into consideration when generating the replacement bit.

10.2.6 CBus interface

CBus

type  name
I TF*  CBus Frame*
I TOT CBus Outbound Tag
I TIT  CBus Inbound Tag
B TD  CBus Data
B TDB CBus Data Branch
I Sync* Sync*
I Reset* Reset*

(10.6)

The following output signals are produced on a permodule rather than per-chip bases, and are handled by a multipurpose pin: CBus Inbound Tag Local (TITL), CBus Outbound Tag Branch (TOTB), CBus Frame Branch* (TFB*), CBus Sync Branch* (TSB*),

1Depending on the setting of the FPL bit in the Hardware Environment Register (§6.20).

Other CBus related signals go through significant onboard conditioning, and are listed in §10.2.7.

10.2.7 Miscellaneous

Miscellaneous

type  name
I Clock  Clock
O MP  Multipurpose
W Int*  Interrupt*
W ModSel Module Select

(10.7)

The Interrupt* pins from the 16 chips of a module are wire-ored together. The resulting signal is merged with Scan-in-Progress information and output on one of the 16 Multipurpose pins (§6.21), to be used, after proper conditioning, as the CBus Status* signal contributed by the module.

The Module Select pins from the 16 chips of a module are wire-anded together, to allow the individual chips to contribute to a module-wide and and sense its result, as explained in §3.13. As each pin will be actively driven immediately before the clock cycle in which the and operation will be performed, the pull-up resistor connected to this wire is only for long-term bleeding purposes,

Reset* and Clock are derived from the corresponding CBus signals. Redistribution of these signals to the tree branches is handled by on-board discrete circuitry rahter than by the stepchip.

10.2.8 Spares, reserved

Reserved

type  name
I Esc0 Escape0
I Esc1 Escape1

(10.8)

The behavior of the stepchip is characterized only when the two pins Escape0 and Escape1 are tied to logical 0.

In some versions of the die used for the stepchip, for fabrication convenience some of the spare die area may have been used for other chips. A scheme presently being considered for this multiplexing of functions on the same die is the following

Esc0 Esc1  chip selected 0  0 stepchip 0  1 ctlsv chip 1  0 fsm chip 1  1 dataregs chip  .  (10.9)

The step controller will use one fsm, two stlsv, and two dataregs chips.