% -*- Mode:Text  -*- 

\chapter{Module board schematics}\label{module-circuit}

\section{Netlist symbolic names}\label{sect.netlist-names}

The module board consists of a multilayer printed-circuit board on
which a number of different {\em components} (integrated circuit,
connector, resistor, test point, etc.) are mounted. Each component has
a number of {\em pins}. The place where a component pin comes into
electrical contact with the board is called a {\em node}.  A set of
nodes such that (a) all nodes of the set are connected to one anoher
via conductive traces, and (b) no other board nodes are connected to
this set is called a {\em net}. A {\em netlist} is a collection of
nets.

A netlist represents a standard way of describing a board's
interconnection topology.

\medskip


In the netlist, nodes on the module board will be identified by a {\em
symbolic} name formed as follows
 $$
	\langle\hbox{component symbolic name}\rangle.
	\langle\hbox{pin symbolic name}\rangle
 $$

\noindent For instance, the node name {\sym Dram7.WE*} refers to the
write-enable pin ({\sym WE*}; see \fig{sram-symb}) of the \dram\ chip
associated with layer 7 ({\sym Dram7}; see \fig{comp-symb}).  For
convenience of tabular alignment, the numeric field that distinguishes
between different instances of the same component type (e.g., the `9'
in {\sym Dram9} will be written in base sixteen, using {\sym A}
through {\sym F} as digits after {\sym 0}--{\sym 9} (cf.\
\fig{comp-symb}).

Connector names in the netlist will appear in a somewhat shorter form
than in the rest of the manual; for instance, the {\sym \bus\ branch}
connector will be called simply {\sym Branch}, and the {\sym XM
glue}--{\sym ZP glue} connectors will be {\sym Glue0}--{\sym Glue6}.
Note that what are treated as functionally distinct connectors may in
practice be just sections of a single connector extending along
the entire motherboard-side edge of the module.

Eventually, all these names may be replaced by shorter, {\em numeric}
names consisting of a component number and a pin number, such as {\sym
U23.9}.

\medskip

The components on the module board are specified in
full in \sect{packages-netlist}


\section{Board components}\label{sect.module-components}

The main components on the module board are
 \begin{itemize}
	\item Sixteen \chip{}s---one per layer.
	\item Sixteen \dram\ chips, each intimately associated
with one \chip.
	\item Eight \sram\ chips, organized as two banks of four
chips each.
	\item Six {\em Glue} connectors.
	\item Three more connectors, namely {\em \bus\ branch},
{\em Data flywheel}, and {\em Local bus}.
 \end{itemize}
	There are also a number of minor components, such as fanout buffers,
terminating resistors, etc.

\fig{comp-symb} list the components on the module board
with their symbolic names.

\figonegiven{comp-symb}{
\begin{tabular}{|l|l|}\hline
    \multicolumn{2}{|c|}{Integrated circuits}\\\hline\hline
	{\sym Step0}--{\sym StepF} & \chip{}s\\
	{\sym Dram0}--{\sym DramF} & \dram\ chips\\
	{\sym Sram0}--{\sym Sram7} & \sram\ chips\\
	\sym Fanout & fanout buffers\\
	\hline\hline
    \multicolumn{2}{|c|}{Connectors}\\\hline\hline
	\sym Local & local bus\\
	\sym Branch & \bus\ branch\\
	\sym Flywheel & data flywheel\\
	{\sym Glue0}--{\sym Glue5} &  glue connectors\\
	\hline\hline
    \multicolumn{2}{|c|}{Resistors}\\\hline\hline
	{\sym Term0}--{\sym TermB} & glue terminator packs\\
	{\sym TermC}--{\sym TermE} & \bus\ branch terminator pack\\
	\hline
 \end{tabular}
}{Components of the \cam\ module board (bypass capacitors
and other power-conditioning components are not included).}
 



\section{\dram\ control}\label{sect.dram-mcirc}

Each of the 16 \chip{}s of a module has complete control over one
1M\by 4 \dram\ chip, which stores the state variables of the
associated layer (\sect{sectors}).  Symbolic pin names for the {\sym
Dram} component, consisting of a \dram\ chip, are given in
\fig{dram-symb}.

\figonegiven{dram-symb}{
 \begin{tabular}{|r|l|r|l|}\hline
 \multicolumn{4}{|c|}{\sym Dram \rm component}\\\hline
	1 & \sym D0 & 20 & \sym Vcc \\
	2 & \sym D1 & 19 & \sym D3 \\
	3 & \sym WE* & 18 & \sym D2 \\
	4 & \sym RAS* & 17 & \sym CAS* \\
	5 & \sym A9 & 16 & \sym OE* \\
	6 & \sym A0 & 15 & \sym A8 \\
	7 & \sym A1 & 14 & \sym A7 \\
	8 & \sym A2 & 13 & \sym A6 \\
	9 & \sym A3 & 12 & \sym A5 \\
	10 & \sym Vss & 11 & \sym A4 \\\hline
 \end{tabular}
}{Pinout of {\sym Dram} component (MT4C4001, 1M\by 4 \dram\ chip).}

\noindent Pins {\sym Vcc} and {\sym Vss} (power and ground) are tied
respectively to the power and ground planes. Pin {\sym CE*} (chip
enable) is hardwired to a logical 0 (leaving the \dram\ chip
permanently enabled). The other pins are directly driven by separate
\chip\ pins.

\medskip

The \dram-control portion of the module netlist is given in
full in \sect{dram-netlist}

\section{\sram\ control} \label{sect.sram-mcirc}

\Cam's lookup tables consist of two totally separate memory banks
(banks 0 and 1). Each bank has sixteen address lines and sixteen data
lines. A bank is realized by four instances of the {\sym Sram}
component (represented by a 64K\by 4 \sram\ chip) called {\sym
Sram0}--{\sym Sram3} for bank 0 and {\sym Sram4}--{\sym Sram7} for
bank 1.  Symbolic pin names for this component are given
in \fig{sram-symb}.

\figonegiven{sram-symb}{
 \begin{tabular}[t]{|r|l|r|l|}\hline
	\multicolumn{4}{|c|}{{\sym Sram} component}\\\hline
	pin & name & pin & name \\\hline\hline
	 1 & \sym A6 & 24 & \sym Vcc\\
	 2 & \sym A7 & 23 & \sym A5\\
	 3 & \sym A8 & 22 & \sym A4\\
	 4 & \sym A9 & 21 & \sym A3\\
	 5 & \sym AA & 20 & \sym A2\\
	 6 & \sym AB & 19 & \sym A1\\
	 7 & \sym AC & 18 & \sym A0\\
	 8 & \sym AD & 17 & \sym D3\\
	 9 & \sym AE & 16 & \sym D2\\
	 10 & \sym AF & 15 & \sym D1\\
	 11 & \sym CE* & 14 & \sym D0\\
	 12 & \sym Gnd & 13 & \sym WE*\\\hline
 \end{tabular}
}{Pinout of {\sym Sram} component (CY7C194, 64K\by 4 \sram\ chip).}

\noindent Each \chip\ contributes one address line and one data line
to each bank.  The control lines, {\tt CE*} and {\tt WE*}, are handled
by the multipurpose pins, {\tt MPA} and {\tt MPB} respectively, of
\chip\ 2 for bank 0 and \chip\ 3 for bank 1 (\cf{multi-summary}).

\medskip

The \sram-control portion of the module netlist is given in
full in \sect{sram-netlist}


\section{Glue}\label{sect.glue-mcirc}

Each \chip\ has six glue pins called {\sym G0}--{\sym G5}, corresponding
to the six physical directions {\sym XM}, {\sym XP}, {\sym YM}, {\sym
YP}, {\sym ZM}, and {\sym ZP}.

For each of the six direction, the sixteen glue signals (one from each
chip) are routed to a separate glue connector (\fig{comp-symb}) having
the pinout of \fig{glue-symb}.  For netlist purposes, the symbolic
names of the {\sym XM glue}--{\sym ZP glue} connectors will be {\sym
Glue0}--{\sym Glue6}.

\figonegiven{glue-symb}{
 \begin{tabular}[t]{|r|l|r|l|}\hline
	\multicolumn{4}{|c|}{{\sym Glue} component}\\\hline
	pin & name & pin & name \\\hline\hline
	1 & \sym G0-A &	2 & \sym G0-B\\
	3 & \sym G1-A &	4 & \sym G1-B\\
	5 & \sym G2-A &	6 & \sym G2-B\\
	7 & \sym G3-A &	8 & \sym G3-B\\
	9 & \sym G4-A &	10 & \sym G4-B\\
	11 & \sym G5-A & 12 & \sym G5-B\\
	13 & \sym G6-A & 14 & \sym G6-B\\
	15 & \sym G7-A & 16 & \sym G7-B\\
	17 & \sym G8-A & 18 & \sym G8-B\\
	19 & \sym G9-A & 20 & \sym G9-B\\
	21 & \sym GA-A & 22 & \sym GA-B\\
	23 & \sym GB-A & 24 & \sym GB-B\\
	25 & \sym GC-A & 26 & \sym GC-B\\
	27 & \sym GD-A & 28 & \sym GD-B\\
	29 & \sym GE-A & 30 & \sym GE-B\\
	31 & \sym GF-A & 32 & \sym GF-B\\\hline
\end{tabular}
}{Pinout of {\sym Glue} component (glue connector).}

To each glue signal there correspond on the glue connector two pins
({\sym A} and {\sym B}), which will be connected to the two elements of
a transmission-line pair.  In the present implementation, the {\sym B}
pin is tied to the module board's ground plane, while the {\sym A} pin
connects with the \chip\ glue pin via a resistor that matches the
impedance of the transmission line (tentatively, 150 $\Omega$).
For each of the six directions, the sixteen resistors are organized as
two 8-resistor DIPs each having the pinout of \fig{term-symb}, where
the two ends of the same resistor are distinguished
by the letters {\sym P} and {\sym Q}.

\figonegiven{term-symb}{
 \begin{tabular}[t]{|r|l|r|l|}\hline
	\multicolumn{4}{|c|}{{\sym Term} component}\\\hline
	pin & name & pin & name \\\hline\hline
	1 & \sym P0 & 16 & \sym Q0 \\
	2 & \sym P1 & 15 & \sym Q1 \\
	3 & \sym P2 & 14 & \sym Q2 \\
	4 & \sym P3 & 13 & \sym Q3 \\
	5 & \sym P4 & 12 & \sym Q4 \\
	6 & \sym P5 & 11 & \sym Q5 \\
	7 & \sym P6 & 10 & \sym Q6 \\
	8 & \sym P7 & 9 & \sym Q7 \\\hline
\end{tabular} }{Pinout of {\sym Term} component (transmission line
termination resistor pack).}

The glue pins are pulled up internally to the \chip, for reasons explained
in \sect{} \memo{check this}.


\medskip

The glue portion of the module netlist is given in
full in \sect{glue-netlist}


\section{Data flywheel}\label{sect.flywheel-mcirc}

As explained in \sect{}, each \chip\ makes all of its scanned data
available on-the-fly, for inspection and possible modification, via
the {\sym Flywheel Data Output} and {\sym Flywheel Data Input} pins.
These signals from all sixteen chips are brought together on the
{\sym Data Flywheel} connector, which for netlist purposes has the
symbolic name {\sym Flywheel}. The pinout of this connector is given in
\fig{data-wheel-symb}.

\figonegiven{data-wheel-symb}{
 \begin{tabular}[t]{|r|l|r|l|}\hline
	\multicolumn{4}{|c|}{\sym Flywheel \rm component}\\\hline
	pin & name & pin & name \\\hline\hline
	 & \sym I0 && \sym O0 \\
	 & \sym I1 && \sym O1 \\
	 & \sym I2 && \sym O2 \\
	 & \sym I3 && \sym O3 \\
	 & \sym I4 && \sym O4 \\
	 & \sym I5 && \sym O5 \\
	 & \sym I6 && \sym O6 \\
	 & \sym I7 && \sym O7 \\
	 & \sym I8 && \sym O8 \\
	 & \sym I9 && \sym O9 \\
	 & \sym IA && \sym OA \\
	 & \sym IB && \sym OB \\
	 & \sym IC && \sym OC \\
	 & \sym ID && \sym OD \\
 	 & \sym IE && \sym OE \\
	 & \sym IF && \sym OF \\\hline
	 & \sym DSV* && \sym ClockOut \\
	 & ... && ... \\
	 & +5V && Ground \\
	 & +5V && Ground \\
	 & +5V && Ground \\\hline
 \end{tabular}
}{Pinout of {\sym Flywheel} component ({\sym Data Flywheel}) connector.}

Since the {\sym Flywheel} connector is meant for experimentation or
specialized applications rather than for everyday use, few onboard
resources were invested on it. It will be up to the user, for
instance, to buffer the output signals according to the load that they
will actually have to drive.

To facilitate interfacing with external circuitry, the {\em Flywheel}
connector brings out a number of timing and control signals, a few
uncommitted multiporpose-pin lines, and several power and ground pins.
In particular, through {\sym Data Stream Valid*} and {\sym ClockOut}, one
is told on which clock cycles the data stream carries valid bits.
{\sym Clockout} is the same signal that is distributed on the
module board to the sixteen \chip{}, and should not be tapped without
due care \memo{Do we really want this? Should we buffer it? Don't we
want a verbatim compy of the module's internal clock rail brought
out to the edge for testing purposes? Or would that risk degrading
the clock signal itself, and we should use a buffer anyway?}

\medskip

The data-flywheel portion of the module netlist is given in
full in \sect{data-wheel-netlist}.


\section{\bus\ branch}\label{sect.tbus-branch-mcirc}

As explained in \sect{}, from a \cam\ box the \bus\ is routed downtree
to other boxes via the {\sym \bus\ branch} connectors. The transmission
lines that carry signals along each branch are driven (or sensed)
directly by the \chip{}s on each modules. The drivers use series
terminating resistors.

For netlist purposes, the symbolic name of the {\sym \bus\ branch}
connector as a board component is {\sym Branch}. The pinout of this
connector is given in \fig{tbus-branch-symb}. See \sect{} for full
names and descriptions of the pins.

\figonegiven{tbus-branch-symb}{
 \begin{tabular}[t]{|r|l|r|l|}\hline
	\multicolumn{4}{|c|}{{\sym Branch} component}\\\hline
	pin & name & pin & name \\\hline\hline
	 & \sym D0-A && \sym D0-B \\
	 & \sym D1-A && \sym D1-B \\
	 & \sym D2-A && \sym D2-B \\
	 & \sym D3-A && \sym D3-B \\
	 & \sym D4-A && \sym D4-B \\
	 & \sym D5-A && \sym D5-B \\
	 & \sym D6-A && \sym D6-B \\
	 & \sym D7-A && \sym D7-B \\
	 & \sym D8-A && \sym D8-B \\
	 & \sym D9-A && \sym D9-B \\
	 & \sym DA-A && \sym DA-B \\
	 & \sym DB-A && \sym DB-B \\
	 & \sym DC-A && \sym DC-B \\
	 & \sym DD-A && \sym DD-B \\
 	 & \sym DE-A && \sym DE-B \\
	 & \sym DF-A && \sym DF-B \\
	\hline
	 & \sym Reset*-A && \sym Reset*-B \\
	 & \sym Sync*-A && \sym Sync*-B \\
	 & \sym Frame*-A && \sym Frame*-B \\
	 & \sym IHIn-A && \sym IHIn-B \\
	 & \sym OHOut-A && \sym OHOut-B \\
	 & \sym Status-A && \sym Status-B \\
	 & \sym Spare0-A && \sym Spare0-B \\
	 & \sym Spare1-A && \sym Spare1-B \\
	\hline
 \end{tabular}
}{Pinout of {\sym Branch} component ({\sym \bus\ branch}) connector.}

The output signals {\sym Reset*}, {\sym Sync*}, {\sym Frame*}, and
{\sym OHOut} ({\sym Outbound Handshake Out}) are driven by multipurpose
pins via series terminating resistors on the {\sym A} side of the
transmission line (the other side is grounded). The data lines, {\sym
D0}--{\sym DF}, are driven in a similar way by the {\sym \bus\ Outbound
Data} lines (one per \chip). The {\sym IHIn} ({\sym Inbound Handshake
In}) input is buffered and fanned out to the {\sym IHIn} pins on the
sixteen \chip{}s. Finally, the {\sym Status} input is picked up by a
multipurpose pin.

\medskip

The \bus-branch portion of the module netlist is given in
full in \sect{tbus-branch-netlist}.


\section{Local bus}\label{sect.local-bus-mcirc}

As explained in \sect{}, through the {\em local bus} the motherboard
circuitry distributes information to the eight modules of a box
and collects information from them. The local bus consists of three
groups of signals:
 \begin{itemize}
	\item \parhead{Tbus local}
	\item \parhead{Raw video}
	\item \parhead{Auxiliary}
 \end{itemize}
	For netlist purposes, the symbolic name of the {\sym Local
bus} connector as a board component is {\sym Local}. The pinout of this
connector is given in \fig{tbus-local-symb}. See \sect{} for full
names and descriptions of the pins.

\figonegiven{tbus-local-symb}{
 \begin{tabular}[t]{|r|l|r|l|}\hline
	\multicolumn{4}{|c|}{\sym Local \rm component}\\\hline
	pin & name & pin & name \\\hline\hline
	 & \sym D0 && \sym V0 \\
	 & \sym D1 && \sym V1 \\
	 & \sym D2 && \sym V2 \\
	 & \sym D3 && \sym V3 \\
	 & \sym D4 && \sym V4 \\
	 & \sym D5 && \sym V5 \\
	 & \sym D6 && \sym V6 \\
	 & \sym D7 && \sym V7 \\
	 & \sym D8 && \sym V8 \\
	 & \sym D9 && \sym V9 \\
	 & \sym DA && \sym VA \\
	 & \sym DB && \sym VB \\
	 & \sym DC && \sym VC \\
	 & \sym DD && \sym VD \\
 	 & \sym DE && \sym VE \\
	 & \sym DF && \sym VF \\\hline
	 & \sym Reset* && \sym Int* \\
	 & \sym Sync* && \sym ModSel \\
	 & \sym Frame* && \sym Clock \\
	 & \sym OHIn && \sym IDE* \\
	 & \sym IHOut && \\
	 & \sym Status && \\
	 & \sym Spare0 && \\
	 & \sym Spare1 && \\
	\hline
 \end{tabular}
}{Pinout of {\sym Local} component ({\sym Local bus} connector).}

   The output signal {\sym IDE*} ({\sym Inbound Data Enable*}) is provided
in order to control the data direction of external bidirectional
buffers (located on the motherboard) on the glue lines.

\medskip

The local-bus portion of the module netlist is given in
full in \sect{local-bus-netlist}.


\subsection{\bus\ local}

As explained in \sect{}, the \bus\ reaches a \cam\ box via the {\sym
\bus\ root} connector.  Circuitry on the motherboard distributes the
bus to the modules via the {\sym Local bus} connectors. In turn, some
of the box's modules may relay the \bus\ downtree via {\sym \bus\
branch} connectors.

Each of the sixteen \bus\ data pins on the {\sym \bus\ local}
connector, {\sym D0}--{\sym DF}, is directly connected to the {\sym
TD} pins of one of the sixteen \chip{}s.

The module input pins {\sym Reset*}, {\sym Sync*}, {\sym Frame*}, and
{\sym OHI} ({\sym Outbound Handshake In}) drive discrete buffers that fan
out their signals respectively to the sixteen chips' {\sym Reset*},
{\sym Sync*}, {\sym Frame*}, and {\sym Outbound Handshake In} pins.

The module output pins {\sym OHOut} ({\sym Outbound Handshake Out}), {\sym
Status}, and {\sym IDE*} ({\sym Inbound Data Enable*}, used to control
the data direction of discrete bidirectional buffers on the
motherboard), are driven by multipurpose pins\footnote
	{On the motherboard, the eight {\sym IHOut} signals coming
from the box's eight modules are {\sc or}ed \memo{check}, and so are
the eight {\sym Status} signals (which have already {\sc or}ed,
internally to the module, the incoming {\sym Status} from the
{\sym \bus\ root} connector with the module's own {\sym Status}). Of the
latter, the ones from slots 1--7 are pulled down on the motherboard by
2 K$\Omega$ resistors, capable of overriding the 25 K$\Omega$ pullups
internal to the \chip.  The one from slot 0, however, is pulled {\em
up} by a 2 K$\Omega$ resistor on the motherboard. The effect of this
pullup is sensed by the interested \chip\ during initialization (on
reset, all multipurpose pins are configured as inputs) and is used to
configure the module in slot 0 as module 0 of the box (``geographical
addressing'').  Subsequently, the {\sym Status} pin is configured as
an output, and it becomes irrelevant whether it is pulled up or down
on the motherboard.}
	(see \fig{bus-control-summary}).

The pinout for the fanout buffers are given in
\fig{fanout-symb}.

\figonegiven{fanout-symb}{
 \begin{tabular}{|r|l|}\hline
	pin & name\\\hline\hline
	 & \sym In \\
	 & \sym Out \\\hline
 \end{tabular}\quad
}{Pinout of {\sym Fanout} component (fanout buffer).}

\memo{Is the fanout buffer for clock the same type as for the other signals?}

\medskip

Finally, there are two \bus-related lines, namely {\sym ModSel}
\memo{Check polarity} and {\sym Int*}, that run along the sixteen
\chip{}s of a module, performing, respectively, a wired-{\sc or} and a
wired-{\sc and} function. These are weakly pulled up by ??? K$\Omega$ resistors.

\memo{Give pinout of Pullup resistor or resistor pack}
\memo{Add Vcc or Gnd end of resistor to netlist}

\subsection{Raw video}\label{sect.raw-video-mcirc}

As explained in \sect{}, there is on the motherboard a sixteen-bit
{\em Raw video} bus (pins {\sym V0}--{\sym VF} of the {\sym Local
bus}) on which one of the eight modules may place (by enabling its
tri-state {\em Raw video} outputs) a word of data intended for
real-time video display. Each of the {\sym V0}--{\sym VF} pins
is wired directly to the {\sym Raw video} pin of one \chip.


\subsection{Auxiliary}\label{sect.auxiliary-mcirc}

As explained in \sect{}, the {\sym Clock} signal distributed by the
motherboard to the eight modules via the {\sym Local bus} connector is
derived from the box's secondary master clock.


\section{Multipurpose pins}\label{sect.multi-summary}

Under program control, each of the two multipurpose pins on each
\chip\ can be configured as an output and internally connected to any
of a number of sources, or configured as an input and internally
connected to any of a number of destinations. Since on the module
board some of the multipurpose pins are dedicated to definite
functions, they are expected to be suitably programmed for these
functions at initialization time, as specified in
\fig{module-mp-functions}; other pins are wired to spare connector
pins and may be dynamically reprogrammed for different functions; the
remaining pins are left unconnected (or may be brought to test points
on the board).

\figonegiven{module-mp-functions}{
 \begin{tabular}{|r|l|l|}\cline{2-3}
	\multicolumn{1}{c|}{}
	  & \multicolumn{1}{c|}{\sym MPA} & \multicolumn{1}{c|}{\sym MPB}\\
	\cline{2-3}\hline
	0 &\bus\ local {\sym Status}
	  & \bus\ local {\sym IHOut} \\
	1 & \bus\ branch {\sym Frame*}
	  & \bus\ branch {\sym OHOut} \\
	2 & \lut0 {\sym Chip Enable*}
	  & \lut0 {\sym Write Enable*} \\
	3 & \lut1 {\sym Chip Enable*}
	  & \lut1 {\sym Write Enable*} \\
	4 & \bus\ branch {\sym Reset*}
	  & \bus\ branch {\sym Sync} \\
	5 & \bus\ branch {\sym Status}
	  & \bus\ local {\sym IDE*} \\
	6 & \sym Data Stream Valid*
	  & \sym Latch Glue Direction* \\
	\hline
 \end{tabular} }{Dedicated-function multipurpose pins on the module
board. The left column gives the \chip\ number. All pins are
programmed as outputs, except for the \bus\ branch {\sym Status} pin,
which is an input.}

The output signal {\sym Latch Glue Direction*} is provided in order to
control the data direction of external bidirectional buffers on the glue
lines. Since these buffers are not needed in the current version of the module,
the {\sym LGD*} line is left unconnected.

Figure \fig{bus-control-summary} summarizes the responsibilities for
the inner and outer \bus\ control signals.

\figonegiven{bus-control-summary}{
 \begin{tabular}{|l|l|l|}\hline
	\multicolumn{1}{|c|}{signal} & \multicolumn{1}{c|}{inner}
	 & \multicolumn{1}{c|}{outer}\\\hline
	\hline
	\sym Reset* & {\sym Reset*} rail & {\sym MPA}, 4 \\
	\sym Sync   & {\sym Sync} rail & {\sym MPB}, 4 \\
	\sym Frame* & {\sym Frame*} rail & {\sym MPA}, 1 \\
	\sym HIn    & {\sym OHIn} rail & {\sym IHIn} rail \\
	\sym HOut   & {\sym MPB}, 0 & {\sym MPB}, 2 \\
	\sym Status & {\sym MPA}, 0 & {\sym MPA}, 5 \\
	\sym LDE*   & {\sym MPB}, 5 & --- \\\hline
	\sym Int*   & \multicolumn{2}{c|}{wire-{\sc and} rail}\\
	\sym ModSel & \multicolumn{2}{c|}{wire-{\sc and} rail}\\
	\hline
 \end{tabular}
}{Summary of \chip\ pin assignment for \bus\ control signals. All
multipurpose-pin signals ({\sym MPA} and {\sym MPB}) are outputs
except right {\sym Status} (which is an input). All rail signals
are inputs, except for the the wire-{\sc and} rails,
which are at the same time inputs and tri-state outputs.}


\memo{Make note of initialization function of Status pin}
 
\endinput
